Design Of Fractional Frequency Divider And Automatic Frequency Calibration For Multi-Mode Multi-Standard Receiver

The rapid development of wireless communication technology and the continual growth of data throughput have expressed increasingly stringent specifications for higher performance and system integration. A signal chip with different wireless standards has a wide application prospect. Hence, multi-band multi-mode support by a signal transceiver chip becomes a heated research spot. Frequency synthesizer with high resolution, pure spectrum and wide tunable range is still imperative for multi-band multi-mode RF transceiver. In this paper, a Fractional-N Frequency Divider (FNFD) and auto-calibration technique in multi-standard Fractional-N Frequency Synthesizer (FNFS) are designed.The fundamental principle of FNFS is introduced in the first place and the transfer function of FNFS is derived through linear approximation of each module. Meanwhile, the loop stability and FNFS output phase noise is analyzed according to the transfer function. In addition, a system framework of wide tunable FNFS is proposed.A FNFD, including high-speed divide-by-2 circuit, programmable frequency divider with 0.5 step size and a △-∑ modulator, is designed in line with design objective. Divide-by-2 circuit, implemented in current-mode logic, is used to generate four orthogonal local oscillating signals. Moreover, the programmable frequency divider employs a phase swithing citcuit and a divide-by-2/3 circuit chain to achieve 0.5step size and wide programmable frequency division range respectively. What’s more, the △-∑ modulator, devised with semi-custom design flow, adopts an advanced MASH 1-1-1 structure to improve output sequence length thus reducing fractional spurs. Furthermore, an auto-calibration technique which consists of an optimal code finder and loop bandwidth calibrator is designed base on frequency comparsion. The optimal code is selected by bineary search and the loop bandwidth calibrator regulates the current of charge pump in terms of the measured VCO gain, in consequence, making the loop bandwidth constant.The FNFD and auto-calibration circuit are implemented in TSMC 0.18μm RF CMOS process, occupying a chip area of 1.0mmx0.58m and 0.17mm×0.18mm repectively. The post simulation results show that the frequency division raitio ranges from 121 to 1016 and FNFD can correctly divide the input signal within 0.4GHz to 8GHz in worst case when consuming 9.51mA current. The frequency resolution of calibration circuit is 5MHz and the total calibration time is 16.6us. The average current consumption of calibration circuit is less than 0.5mA. The designed FNFD and auto-calibration circuit have been applied in a wide tunable FNFS, further test is needed in the follow-up work.