Design Of Fractional Frequency Divider In Multi-mode Multi-standard CMOS Phase Locked Loop Frequency Synthesizer

With the rapid development of modern wireless communication technology and the regeneration of communication devices,wireless communication system with multi-mode multi-standard has a wide application prospect and practical demand.Hence,the design of multi-mode multi-standard RF transceiver becomes a heated research spot.As a significant module of RF transceiver,frequency synthesizer can provider local oscillator signal to both transmitter and receiver,so its quality is directly related to the performance of the whole transceiver.In this thesis,Fractional-N Frequency Divider(FNFD)which is the key module of Fractional-N Frequency Synthesizer(FNFS)is researched and desgined.The fundamental theory and principle of FNFS is introduced in the first place and the transfer function of FNFS is derived through linear approximation of each module.Then,the loop stability and FNFS output phase noise is analyzed according to the transfer function.The structure of FNFD in the thesis contains three modules,including high-speed divide-by-2 circuit,programmable frequency divider with 0.5 step size and a ?-? modulator.The high-speed divide-by-2 circuit is desgined by source coupled logic structure,and it has a wide operating frequency range(1 GHz to 8 GHz).It can generate four orthogonal oscillating signal.The programmable frequency divider with 0.5 step size consists of a phase switching circuit and an integer-N programmable frequency divider.The phase switching circuits completes 0.5 step size by switching the output of the eight signals,which can effectively decrease quantization noise of circuit.The integer-N programmable frequency divider is achieved by five divide-by-2/3 circuits and its frequency division ratio can be extended by logic gates.It can generate programmable division ratio from 4 to 63.The ?-? modulator is designed by semi-custom flow,and adopting an original HJ-MASH 1-1-1 structure with long output sequence length,which has better spurious rejection and strong structure stability.The FNFD is designed with TSMC 0.18?m RF CMOS process,occupying a chip area of 1.10 mm ×0.54 mm,the post simulation results shows that under the worst case,It can correctly divide the input signal with 0.4 GHz to 8.3 GHz,the frequency division ratio ranges from 32 to 504,and the total current consumption is 9.20 mA,which meet the requirements of this project.