Used In The Research And Design Of Multi-mode Wireless Communication Receiver Frequency Synthesizer

As a first step toward Software-Defined Radio (SDR), frequency synthesizer for cellular and short range multi-standard wireless receiver is studied in this thesis. The purpose is to demonstrate the design procedure of frequency synthesizer in multi-standard communication system.Specifications for frequency synthesizer are firstly described, and then method of mapping from standard to circuit specifications is presented.Specifications such as phase noise, spur, settling time of frequency synthesizer are interpreted from standards of DCS1800, WCDMA, Bluetooth, and so on by this method.Based on the acquired specifications, architecture of the designed frequency synthesizer is proposed after comparing state-of-art circuits in multi-standard receivers.Starting from stability of PLL, loop parameters design procedure constrained by phase noise, spur and settling time is presented.Discussion of circuits design for frequency synthesizer is presented in detail.An optimally coupled QVCO is proposed to improve performances of oscillator. A detailed timing diagram of programmable divider is presented to study design technique of programmable divider in fractional-N frequency synthesizer. Design of other building blocks such as charge pump, harmonic rejection SSBmixer, automatic frequency calibration circuit, and so on is also presented.A frequency synthesizer is designed and implemented in TSMC0.13μm CMOS process to verify the design idea. Measurement results are presented and show that the output frequency range of this frequency synthesizer covers operating frequency bands of DCS1800, WCDMA, TD-SCDMA, Bluetooth, and WLAN802.11a/b/g. The settling time is less than 50μs. Measured phase noise at frequency range 1.8GHz-2.5GHz achieves less than-120dBc/Hz at 1MHz and about -90dBc/Hz at 100 kHz. Phase noise at frequency range 5GHz-5.8GHz achieves less than-115dBc/Hz at 1MHz and about-86dBc/Hz at 100 kHz. Loop bandwidth of frequency synthesizer is 90 kHz, and the reference spur at 40MHz is less than-60dB while the fractional spur at 1 MHz is-71 dB.