Research And Design Of Fractional Divider

With the rapid development of wireless communication system, monolithically integrated frequency synthesizer for local oscillator signal, as an important part of the communication system, has become increasingly important. As a critical part of the frequency synthesizer, the fractional divider seriously affects the output frequency accuracy, phase noise, locking time and reference spur. Among the structures of fractional-N divider, Sigma-Delta Modulator Fractional-N divider, due to its low noise and easy to implement, has become the mainstream of the design and application of the fractional-N frequency synthesizer.The fractional-N divider applied to the frequency synthesizer was studied and designed in this paper. First, the influence of the fractional-N divider on the frequency accuracy, phase noise and locking time of a frequency synthesizer is analyzed on the system level. Based on the above analysis, the SCL and TSPC structures of D flip-flop are elaborated and applied to structure the dual modulus dividers and multi-modulus dividers. Finally, the Sigma-Delta modulators including first-order, single-loop and MASH structure are analyed based on the oversampling and noise shaping theory. The specific circuit was given and work process of the modulator is described in detail.An integer/fractional-N frequency divider with division ratio ranging from132to1020was implemented in SMIC65nm RF CMOS process. The divider is composed of a multi-modulus divider based on SCL D flip-flops and a MASH1-1-1Sigma-Delta modulator. Multi-modulus divider adopts cascaded divided by2/3dual modulus divider. In order to produce fractional mode divider,24bit MASH1-1-1structure Sigma-Delta modulator is adoped to control the multi-modulus divider to generate random division ratio. The power consumption and area are optimized in the paper. The divider was designed and simulated from schematic level to layout level. With the impact of the Sigma-Delta modulator, the divider’s fractional mode divide step is1/224in theory. From the results of the simulation and measurement, the division ratio ranges from132to1020and the divide step is1in interger mode. The divider can operate from600MHz-6GHz when a differential sinusoid signal with Vp-p larger than400mV is applied.In order to reduce the chip area and reduce cost, the SPI bus is designed to configure the divider. Sigma-Delta Modulator and SPI slave are the digital part of the fractional divider. They are synthesized from register-transfer level to layout level by EDA tools. The post layout simulation of digital circuit is done by Modelsim. At last, the mixed signal simulation and whole layout of the fractional divider are given out. The fractional divider has been applied to a fractional-N PLL. Test results show that the fractional-N PLL workes properly and exibits good performances. It can be concluded that the designed divider works well and satisfies the design requirements.