Design Of Key Modules And Systematic Optimization For Multi-mode CMOS Frequency Synthesizer

With the continuous development in wireless communication modes,it has become a trend of the wireless communication technology to integrate various communication modes in a mobile terminal.RF transceivers capable of operating at different wireless standards have become a hot spot as well.As a key part,frequency synthesizer determines the performance of the whole wireless transceiver.In this thesis,key modules as well as systematic optimization of multi-mode CMOS frequency synthesizer are designed.This thesis firstly introduces the basic principle and every sub-module of phase-locked-loop(PLL)based fractional-N frequency synthesizer,as well as deduces the transfer function and establishes the linear model of the system.Then,the loop stability,the dynamic characteristics and the noise performance are analyzed according to the linear model.Also,a system framework of fractional-N frequency synthesizer is proposed.The fractional-N frequency divider designed in this thesis includes a high-speed divide-by-2,a programmable integer-N frequency divider and a ?-? modulator.The high-speed divide-by-2,implemented in source-coupled logic,is used to generate four orthogonal local oscillation signals.The programmable integer-N frequency divider consists of a divide-by-4 and a divide-by-2/3 chain whose frequency division ratio can be extended by logic gates.The ?-? modulator,used to shape the quantization noise,is achieved by an improved MASH 1-1-1 structure to improve the output sequence length and reduce the fractional spurs.Furthermore,an auto-frequency calibration circuit,which includes an optimal code finder and a loop bandwidth calibrator,is designed on account of frequency comparison.The optimal code is selected by binary search algorithm,while the loop bandwidth calibrator regulates the current of the charge pump in terms of the frequency division ratio and VCO gain to achieve the constant loop bandwidth.The fractional-N frequency synthesizer is optimized in this thesis according to hybrid FIR noise filtering technique.The output control signals from the ?-? modulator with delay units pass 8 parallel programmable integer-N frequency dividers and PFDs respectively,and they are finally added by an 8-input programmable charge pump in analog domain.The hybrid FIR noise filter can offer full-customized noise shaping,as well as a unit DC gain to solve the noise amplification.The whole fractional-N frequency synthesizer is designed in circuit and layout based on TSMC 0.18?m RF CMOS process,occupying a chip area of 1.22x 1.07mm2.The ?-? modulator and the auto-frequency calibration circuit are devised with semi-custom design flow while the other modules are devised with full-custom design flow.The post-simulation results show that the frequency division raitio of the fractional-N frequency divider ranges from 32 to 504.The fractional-N frequency divider can correctly divide the input signal from 0.4GHz to 8.0GHz in the worst case,while consuming 7.65mA current.For the auto-frequency calibration circuit,the total calibration time is 16.2?s,the frequency resolution is 5MHz and the average current consumption is less than 0.5mA.The simulation results show that the fractional-N frequency synthesizer covers a frequency range from 0.923GHz to 7.681 GHz while the frequency resolution is 20Hz.The total lock time is less than 40?s,and the operation current is less than 23mA.As a result,the fractional-N frequency synthesizer designed in this thesis can meet all the requirements.