Design Of Fractional-N Frequency Divider For Multi-Standard Wireless Transceiver

With the rapid development of wireless communication modes and communication terminals, integrating various communication modes in a mobile terminal has become the trend of the wireless communication technology. Because of this, multi-standard wireless transceiver has become the hot spot of current research. As the key part, frequency synthesizer not only determines the performance of wireless transceiver, but also makes multi-standard wireless transceiver more fully integrated. Frequency synthesizer can provide multiple frequency signals with high precision by changing the frequency division of Fractional-N frequency divider. So that Fractional-N frequency divider is a very important module in frequency synthesizer. In this paper, a Fractional-N frequency divider is designed, which can be used in multi-standard frequency synthesizer.This thesis firstly introduces the basic principle and every modules of Fractional-N frequency synthesizer. Then the performance indicators are analyzed. Meanwhile, the linear phase noise model of PLL (Phase Locked Loop) in locking status is established and the noise of each block with the noise transfer function is derived. In addition, the whole structure of frequency synthesizer is given. According to the analysis, a Fractional-N frequency divider is designed, which consists of a high-speed divider-by-2, a programmable frequency divider with 0.5 step and a △-∑ modulator.The first high-speed divider-by-2 works at the highest frequency and it uses SCL (Source Coupled Logic) structure. The high-speed divider-by-2 has a very wide operating frequency range. The programmable frequency divider with 0.5 step is composed of a high-speed divider-by-2, a phase switching circuit, an integer-N programmable frequency divider and a logic control module. The second high-speed divider-by-2 provides 4 orthogonal signals for phase switching. The integer-N programmable frequency divider is based on a chain of divider-by-2/3 and its frequency division ratio can be extended by logic gates. In this paper, the integer-N programmable frequency divider can generate programmable division ratio from 32 to 127. Logic control module controls the number of phase switching to realize 0.5 step. △-∑ modulator is achieved by an improved MASH 1-1-1 structure, which cascades three first-order error feedback modulators. Compared to the traditional structure, the improved error feedback modulator can receive front-level’s quantization noise and final output. As a result, the output sequence length can be increased and the fractional spurs can be reduced. △-∑ modulator uses standard cell design.The whole Fractional-N frequency divider is implemented in TSMC 0.18μm RF CMOS process, occupying a chip area of 1130μm×510μm. It has been taped out. With 1.8V supply voltage, the measure results show that it can correctly divide within the frequency range of 0.8～9GHz. Its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.The multi-standard Fractional-N frequency divider designed by this thesis is of valuable reference for wireless communications, satellite navigation, wireless sensor network and other applications.