Design And Optimization Of CMOS RF Frequency Synthesizers

The ever growing need for convenient and portable wireless communication equipmentsdemands low cost and high performance wireless transceiver design. This thesis discusses theresearch on the RF frequency synthesizer, the critical building block in modern wirelesstransceivers.Modern RF frequency synthesizers face many design challenges, including compensationfor wideband voltage-controlled oscillator (VCO) gain variation, low power divider,quantization noise suppression in ΔΣ modulator, and fast settling. All of these designchallenges are discussed and novel design techniques are presented to improve theperformance and power consumption of the RF frequency synthesizers.An overview of CMOS RF frequency synthesizers is presented first, covering thefundamental theory of the frequency synthesizer and its basic building circuit blocks,including the VCO, the frequency dividers, the charge pump (CP), the phase-frequencydetector (PFD), and the loop filter. The loop/noise models of both integer-N and ΔΣfractional-N frequency synthesizers are analyzed.The design of VCO is discussed in Chapter3. Three different phase noise models andsome noise optimization guidelines are given with respect to individual circuits. The selectionstrategy between passive and active components of wideband LC-VCO is given. Thecompensation for wideband VCO gain variation is analyzed and a novel technique, i.e., linearregion extension method, is proposed to mitigate the problem. A design example and silicontest results are presented and it is shown that the gain variation is reduced to within5%using the proposed technique.The frequency dividers consume a large portion of the total power in RF frequencysynthesizers. The injection-locked frequency dividers (ILFD) can be utilized in frequencysynthesizers to achieve ultra-low power consumption. Chapter4discusses the advantages anddisadvantages of ILFD used in frequency synthesizer. A new circuit implementation of ILFD,with self-biasing scheme, is proposed to mitigate the shortcomings associated with traditionalILFD circuits, including narrow locking frequency range and high sensitivity to biasingconditions. Adaptive dual-modulus ILFD is also proposed to extend the usage of ILFD inmulti-modulus dividers.The influence of quantization noise in ΔΣ fractional-N frequency synthesizers isthoroughly analyzed and discussed in Chapter5. The quantization noise can be suppressed byreducing division interval of dividers. A novel glitch-free phase switching multi-modulusfrequency divider (PS-MMFD) is proposed to achieve half-step division and thus quantizationnoise suppression. Detailed implementation and silicon test results of the proposedPS-MMFD are presented as well.Design techniques for fast settling frequency synthesizers are discussed in Chapter6.Two approaches are proposed to achieve fast settling of ΔΣ fractional-N frequencysynthesizers. The first one utilizes an automatic frequency calibration (AFC) with anoptimized algorithm and digital implementation. The second one utilizes a novel PFD/CPcombination with linear region extension technique, which solves the cycle slip problem infrequency synthesizers.Chapter7presented a design example of ΔΣ fractional-N frequency synthesizer in0.18μm CMOS technology, targeting for China Mobile Multimedia Broadcasting (CMMB)tuner applications. The chip area is about2.1mm×0.92mm including digital logic and pads. Itconsumes totally10mA from a supply voltage of1.8V. Silicon test results show that theintegral phase error is less than0.52degree, reference spur is better than-80dBc, and the worst case settling time is less than50μs, meeting the stringent CMMB applicationrequirements.