| With the rapid development of integrated circuit manufacturing technologies,the feature sizes and working voltages of circuits show a decrease tendeny,and the amount of critical charge required for logic changes of nodes in circuits also decreases.As a result,integrated circuits and systems are more and more vulnerable to single event effects,which can cause soft errors.Under the charge sharing mechanism,the fact that a particle strikes a node pair in a circuit can induce a double-node upset(DNU),which is a typical soft error.Nowadays,static random access memory(SRAM)plays an important role in integrated circuits.However,SRAM cells are becoming more and more sensitive to single event effects,and thus their reliability is becoming a serious challenge.This thesis analyzes the features and working principles of existing SRAM cells,and proposes SRAM cells protected against DNU.The main research work of this thesis is as follows:(1)A sextuple cross-coupled SRAM cell(namely SCCS)with optimized access operations is proposed.Any node of the cell can self-recover from any single event upset(SEU)and can tolerate a part of DNUs.Compared with typical existing radiation hardened SRAM cells,the SCCS cell can save 61.47% read access time and 11.61% write access time on average,at the cost of extra silicon area and power dissipation.(2)The DNU-completely-tolerant memory(DNUCTM)and DNU self-recoverable memory(DNUSRM)cells are proposed.Any node of the DNUCTM cell can self-recover from any SEU and can tolerate a part of DNUs.In addition,the DNUCTM cell uses a layout-level hardening technique to improve its protection against all possible DNUs.Compared with typical existing radiation hardened SRAM cells,the DNUCTM cell can save 55.60% read access time and 33.76% write access time on average,at the cost of extra silicon area and power dissipation.For the proposed DNUSRM cell,any node pair of the cell can self-recover from any DNU.The DNUSRM cell is more reliable but still at the cost of more silicon area and power dissipation. |
