| Profit from multi-step conversion and pipelining, Pipeline ADC gives attention to speed, accuracy, power dissipation and area simultaneously, and it is widely used in wireless communication and video processing fields. In this thesis, based on the requirement of Deep-Submicron CMOS Image Sensor System, key issues about pipeline ADC design are presented. It analyses the effect of capacitor mismatch, finite OTA gain and bandwidth, comparator offset, nonideal analog switch and so on. The design of main circuit blocks such as OTA, comparator, switch is also introduced in detail. A 12bit 50MSample/s pipeline ADC with high dynamic performance is designed and validated by simulation.In the thesis, a methodology leading to easy design of fast-settling OTA with Ahuja-Style compensation is presented. In contrast to previous works which focus on the OTA's close loop transfer function, a simplified open loop transfer function is deduced and a set of system parameters represent the location of open loop poles and zeros are extracted. Using mathematics software, a graph is made to reveal the relationship between system parameters and settling time. In this way, the optimal value of the system parameters that minimize the settling time can be found out easily. A series of simple equations are given to derive device parameters from system parameters. Simulation results validate the proposed method.In the design of 12bit 50MS/s ADC, an innovative voltage shift circuit is used in the sample and hold amplifier, and it has better frequency responds than normal one formed by source follower. The residue amplifier is formed by the Ahuja compensated two stage OTA with a slew rate enhancement circuit which is designed to improve the large signal response of the amplifier and reduce power dissipation. The design of the DAC in the first stage keeps the common mode input voltage level of the residue amplifier constant, thus the requirement of the OTA's common mode input range is loosen. |
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