For Low Supply Voltage, High-performance Pipelined Adc Realization

In the last decades, with the rapid development of wireless communication technology, the analog circuits design confronts more and more challenges. In the condition of advanced process, high-speed high-performance mixed signal circuit becomes the hotspot of the current research. For ADCs widely used in RF receiver, high sampling rate, high resolution, high speed, low power are always the objects of the circuit design. At the same time, taking into account the cost of the chip, more and more circuit blocks even the whole system are realized in one wafer. This results the analog circuits and digital circuits sharing the same supply voltage. In order to reduce dynamic power, the digital circuits lower the supply voltage. It makes the analog circuits design more difficult.This paper proposed a high speed high resolution pipeline ADC for video application. Some innovation in circuit and system level has been proposed to solve the challenges of lower supply voltage in advanced process.The main innovation of this paper is as follows:(1) A novel pipeline architecture of stage 0 is proposed. It reduces the output swing of each stage half of the original value, which makes the gain-boosting OTA used in pipeline ADCs become possible.(2) A novel synchronization sampling strategy is proposed. A SHA-less pipeline ADC becomes possible. It saves power and reduces thermal noise. It also meets the requirement of innovation one for low output swing.(3) A novel low-offset dynamic comparator for high-speed low-voltage pipeline ADCs is proposed. As the core of subADC, the whole solution program for the whole system operating in low supply voltage has been achieved.(4) A novel circuits and systems design method which uses verilog-a as an aid is proposed. It can accelerate the design process and improve efficiency.