Design Of A Hybrid Structure Analog Digital Convertor Applied In DSP

With the rapid development of semiconductor technology,the degree of digitization and integration of chips are continuously increasing,and the power consumption is continuously decreasing.In order to meet the needs of large-scale embedded integrated system,how to reduce area and power consumption,improve accuracy is a hot spot in the research and design of today's Analog-to-Digital Converters(ADC).This thesis first conducts a systematic analysis of the Digital Signal Processor(DSP)applications it faces and determines design indicators of ADC;then,based on the low power requirements of DSP,analyzing power consumption sources of traditional pipeline ADC;finally using“4+6+4”three-stage pipeline structure to designing a 12-bit ADC.Combined with the front-end structure without sample and hold amplifier and op amp sharing technology,the number of op amps used in ADC system is reduced to one,so as to achieve the purpose of low power consumption;at the same time,the middle stage uses Subranging SAR(Pipeline+SAR)structure to reduce the number of comparators in three-stage pipeline structure.The front-end structure without sample-and-hold op amp brings about input range reduction and aperture error problems.First,the traditional switched capacitor comparator is improved to increase the input range to meet the quantization range of 0-3.3V full power supply voltage required by the DSP system;secondly,through improving the matching of signal paths to reduce the aperture error within calibratable range.Based on the GSMC 0.13?m 1P6M process,under the Cadence platform,the circuit design simulation and layout work are completed,and finally the test work of chip is completed.The ADC occupies a chip area of 1.1×1.3mm~2.Measurement results with a 36.0546875KHz input wave under a sampling rate of 4.615MHz show that the ADC achieves a 65.97-d B signal-to-noise and distoration ratio(SNDR),a76.2-d B spurious-free dynamic range(SFDR)while consumes the power consumption of 43m W.