10bit 50M Sampling Frequency Pipeline ADC Design

As technology develops,the function of the integrate circuit becomes more and more strong,system-on-a-chip which analog and digital circuit can be made on a one chip is the development objective.How to design an ADC which meets technical parameters and have high compatible with digital process is the key emphases during the design.Pipeline ADC structure is chosen at last after a large number of ADC structures are analyzed and compared.It is al.5bit/stage pipeline structure with 9 stages.There are several characters in the circuit design:high-speed,high-gain OTA and bootstrap sample switches are used together in Sample/Hold circuit to improve accuracy and linearity;A new method is used in the design process of current mode bandgap to improve accurate class;Combination bandgap and voltage buffer as voltage reference circuit in chip to provide voltage reference for the other circuits in the ADC.Optimized bias circuit improve consistentcy and stability with OTA;Two-phase non-overlapping clock generator increases clock cycle utilization;A dynamic voltage comparator is used to increase speed and decrease power consumption,it's direct current power consumption is almost zero.This ADC chip is fabricated in SMIC 0.18μm 1P6M CMOS process which power supply is 1.8V,the whole circuit simulated by HSPICE.OTA open loop gain is 100dB,phase margin is 68.8 degree,unit gain bandwidth is 445MHz.3dB bandwidth is 147KHz,set-up time less than 6ns.The pipeline ADC contain the OTA have 9 stages pipeline and achieves 10bit resolution.The whole chip die area is 1.4*1.4 mm2...