Key Techniques For High-resolution Intermediate Frequency Sampling Pipeline Analog-to-digital Converters

The speed and resolution of an Analog-to-Digital Converter(ADC) characterize the performance of control system in real world. For given area and power efficiency, pipeline ADC is an excellent architecture to achieve both high sampling rate and high resolution simultaneously. Further, modern IF-sampling superheterodyne communication system requires ADCs to sample input signals up to 300 MHz in order to reduce receiver complexity and lower overall system cost. Pipeline structure is a good choice for ADCs used in such wireless communication systems, and ideally suited for realizing 12-16 bits of resolution, 70-80 d B of SNR, 85-95 d B of SFDR at 100-300 MS/s, while dissipating less than 1W of power. Therefore, it is very important and necessary to study key technologies of the high-resolution IF-sampling pipeline ADC.By analyzing the error sources in real switch-capacitor pipeline ADC, the thesis studies key technologies of the pipeline ADC. An example is given out to illustrate the method proposed in this thesis. Firstly, the thesis expatiates IF sampling theory and basic principle and error sources of pipeline ADC in real world. Then methods and suggestions for diminishing and eliminating these errors are described. Finally, a 14-bit 250MS/s pipeline ADC is implemented to prove the method proposed. As amplifier is one of key modules in pipeline ADC, a valid design method for short-channel CMOS amplifier is introduced. Meanwhile, in a pipeline ADC, interconnection between stages is complicated and parasitic parameters have negative impact on system performance, especially if the input signal frequency is high. Therefore, it would be particularly important for the layout of the IF-sampling ADC. A method for layout design is proposed in this thesis to resolve parasitic and symmetry issues of sample capacitors and interconnections in pipeline ADC.A 14-bit 250MS/s pipeline ADC in SMIC 0.18μm 1P6 M 1.8V standard CMOS process is presented in this thesis, including ESD pads, the total area is 3.55×3.25mm2 with an active area of 2.5mm2. This ADC achieves an SNDR of 80.12 d B, an SFDR of 98.41 d B with an 11.04 MHz 1.5V sinusoidal signal, while maintaining an SNDR of 79.41 d B, an SFDR of 97.95 d B up to 170.71 MHz input signals.When the input frequency is up to523.25 MHz, which is higher than sampling frequency, 79.09 d B SNDR, 95.47 d B SFDR and 12.84 bit ENOB are obtained. The results show that the ADC meets IF band-pass sampling system design requirements.