Design Of Pipeline-SAR ADC Based On High Linearity And Low Power Interstage Amplifier

Analog-to-digital converter(ADC)plays an irreplaceable role in signal transmission and processing.As the performance factors of the ADC continue to develop in the direction of high speed and low power consumption,Pipeline-SAR ADC has the advantages of high sampling rate of Pipeline ADC and low power consumption of Successive Approximation Register ADC.Therefore Pipeline-SAR ADC has received extensive attention and research in recent years.The residue amplifier is an important part of the Pipeline-SAR ADC,and its gain linearity directly affects the quantization accuracy of the ADC.Therefore,in this paper,after comparing the working principles and advantages and disadvantages of several common residue amplifiers,the dynamic amplifier with high energy efficiency which has no significant short board on the linearity performance is selected as the inter-stage residue amplifier.This article analyzes the factors that destroy gain linearity in traditional dynamic amplifier structures,and performs innovative optimizations on its structure.Pre-simulations and post layout simulation show that its gain linearity has obvious advantages compared to existing structures.The Pipeline-SAR ADC in this paper requires a higher sampling rate.The quantization time of the sub-ADC built by SAR ADC fluctuates greatly,and synchronous timing control cannot be used.Therefore,this paper proposes an asynchronous timing logic control scheme with high stability and high timeliness,so that the sampling rate of Pipeline-SAR ADC can reach 800 MHz even if in ss process.This article finally realized a 14-bit 800 Msps Pipeline-SAR ADC based on Global Foundry 22 nm SOI CMOS process with a power supply voltage of 0.8V.The circuit contains a total of four SAR ADCs cascaded by three highly linear dynamic amplifiers.The simulation results show that when the sampling rate is 800 MHz,the input signal frequency is 80 MHz,and the input range is ±0.77 V,the effective number of bits(ENOB)at any process corner reach more than 12 bit,on tt process corner,the effective number of bits(ENOB)reaches 12.28 bit,and the spurious-free dynamic range(SFDR)reaches 84.7dB,power consumption of analog core circuit is only 28.9mW,FoM is only 7.3fJ / Conv-step.Under the premise that the quantization accuracy of the first-stage SAR ADC is only 4 bits,and the amplification time of the first-stage dynamic amplifier is only 150 ps,the innovative high-linearity dynamic amplifier proposed in this paper exerts a great linearity advantage and effectively improves the signal to noise plus distortion ratio(SNDR)of the ADC.