| A high-speed low-power pipeline A/D converter is designed in this paper. The converter employs the calibration techniques, namely, digital error correction concepts and uses an eleven-stage architecture, by which high precision comparators are not required to reach 12-bit resolution and the converter has a good tradeoff between conversion speed and power. About the architecture of ADC, a new point of view is used. Analyzing the nonideal factors at the beginning and with improving all of this one by one the architecture of ADC is got. About the design, two most important circuits, the op Amplifier and the comparator, are analyzed detailedly and designed. (1) The gain-boosted telescopic architecture is used to ensure the op has a very high dc gain together along with a high unity-gain bandwidth and low power dissipation. (2) A differential pair dynamic comparator which has no DC power dissipation is used in SUB-ADC. The measures above reduce power dissipation effectively. During the design, a charge pump is also used to boost clock voltage to 5v to reduce the conducting resistance of NMOS switches and the effect of charge injecting. All modules in the ADC are stimulated individually and the ADC is stimulated at a system level. The main performance parameters of the ADC are: 12-bit resolution, maximum 40-Msample/s sample rate, power dissipation of 85mW. This chip can be used in video-signal process and portable communication field or embedded in SOC chip as an IP core.
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