Research And Design Of A 12-bit Low Power SAR ADC

With the development of portable electronic terminal equipment,biomedical equipment and wireless sensor networks,the acquisition and processing of signals become entirely significant.As the key part of the signal conversion system,ADC(Analog-to-Digital Converter)requires a longer power supply time with low power consumption design.Among various kinds of ADCs,the SAR(Successive Approximation Register)ADC has a good performance in trade-off between power consumption and accuracy.SAR ADC has the characteristics of simple structure,small area and low prower dissipation,so it is suitable for satisfying the need of low power consumption and low to medium accuracy.The SAR ADC is mainly composed of a DAC capacitor array,a comparator,and a digital logic circuit of the SAR.The DAC capacitor array has a great influence on the power consumption and linearity of the overall circuit.This thesis will have further research on DAC capacitor arrays and other module circuits.This thesis designs a pseudo-differential 12-bit SAR ADC with a sampling rate of 100 k S/s under a 1.2V supply voltage.In consideration of the capacitance value of traditional DACs increases exponentially with accuracy,not only the conversion speed is affected,but also the capacitor mismatch causes nonlinear errors.This thesis proposes a RC hybrid DAC with 4-bit resistance and 8-bit capacitive,which reduces the area of the circuit and improves the integration of the circuit.Monotonic input will reduce the linearity of the circuit,and differential input will increase the power consumption of the circuit.This thesis proposes a pseudo-differential input structure to improve linearity and reduce the power consumption of the overall circuit.Under the condition of low power supply voltage and low sampling rate,the double-boosted sampling switch is used to improve the accuracy of the sampling signal.The addition of timing switches in the comparator circuit can decreasingly reduces the power consumption of the overall circuit.A Programmable cell(Pcell program cell)script have been written in skill language for layout of DAC capacitor array.The DAC capacitor array can be completed by setting the length and width values of the unit capacitor and the number of rows and columns of the capacitor array Automatic layout.Through this method,the drawing efficiency have been improved,and the matching of the capacitor array layout is also ensured.This thesis designs the circuit and layout based on the SMIC 0.18?m process.The digital part and the analog part of the circuit both use a 1.2V power supply voltage.The core area of the chip is410?m ?435?m.The results of post-simulation experiments show that when a 49.96 k Hz sine wave is input,the designed SAR ADC has a spurious free dynamic range of 68.63 d B,a signal-to-noise distortion ratio of 62.37 d B,an effective number of bits of 10.07 bit,and overall power consumption75.85?W.