Low Power Consumption SAR ADC

Digital signal processor (DSP) has been widely used today in integrated circuit (IC) area instead of analog signal processor. As a bridge between analog world and DSP, more and higher performances are required on analog to digital converter (ADC). The commonly used structures of ADC include flash, pipeline, over-sampling (sigma-delta), and successive approximation register (SAR). Among them SAR ADC is mostly preferred because of simple structure, low cost, middle to high resolution and fine compatibility with COMS technology. As the study on SAR ADC is going on, more and more structures are created and used on different applications.In this thesis, first we introduce and compare different structures of ADC. Then we analyze every module of SAR ADC, compare different structures of SAR ADC based on improvements of DAC module, and give quantitative analysis.The target of this thesis is to find a certain structure of SAR ADC which can achieve the requirement of 40Ms/s,12bit, less than 2mW power consumption. Based on the analysis above, we improve and decide a certain capacitance array of DAC, analyze the design of asynchronous control circuit, choose and give a quantitative analysis of the comparator.