Study And Design For A Low Power Successive Approximation Register ADC

Successive Approximation Register Analog-to-digital converter is a common architecture for moderate to high resolution applications requiring the low sampling rate such as less than 5 Ms/s. for the own advantages of simple structure, small size, and low power consumption, it is widely used in many applications, for instance, portable instruments, pen input quantization, industry control and data/signal collector etc. Comparing to Flash ADC, the chip area and number of comparators are exponential proportion to the resolution N in Flash ADC, thus it requires more area and power dissipation. Comparing to Pipelined ADC, Pipelined ADC has a relative more complicated structure. Comparing to Over-sampling ADC, due to the sampling clock limitation, Over-sampling ADC usually limited to moderate or low frequency such as audio applications, which require low conversation speed. Therefore, Successive Approximation ADC with low power consumption, high resolution and small area prefer to be integrated in a more complicated circuit.In this thesis, we design a fully differential CMOS SAR ADC for an ammeter. It is based on Huahong NEC0.35um 1P4M process, using novel Charge Redistribution architecture, thus characterized by small area and low power. We analyze every factor which may affect the resolution of Charge Redistribution SAR ADC, demonstrate the effect which may cause by parasitic capacitors in detail, and propose several conclusions which can also be used in the design of other type high resolution SAR ADC. The design is simulated and layout with EDA tools in Cadence. The simulation results indicate that the effective accuracy is 13.26 bit and the sampling rate can reach 294.1 Ks/s under different combination of corners and temperature ranging from 0 to 120 degree. The total power consumption is about 6.275 mW.