24GHz Millimeter Wave PLL

With the increase of people's demand for communication and the development of 5G communication technology,the phase-locked loop frequency synthesizer,as a key module in the radio frequency transceiver,has become a research hotspot in recent years.In recent years,the CMOS process has been shrinking in feature size and gradually improving performance.In terms of cost and integration,it has advantages over Ga As and In P processes,and has gradually become the mainstream process of millimeter wave integrated circuits.However,the drop in standard voltage also makes some non-ideal characteristics become prominent.Therefore,aiming at these difficulties,a 24 GHz millimeter wave phase-locked loop was researched and designed and verified by simulation.The paper introduces the system composition and related design indicators of the phase-locked loop.A linear model of the loop is established through Matlab&Simulink.The loop characteristics and noise transfer function are analyzed based on the third-order phase-locked loop.Behavior-level simulation is performed to determine the stability of the loop And loop parameters.Analyze the basic principles of each module to optimize the key performance.The main achievements are as follows:1)Millimeter-wave LC-VCO with low power consumption and low phase noise.The biggest feature of this VCO is the current multiplexing structure,which greatly reduces the power consumption of the VCO.At the same time,a high Q MOM capacitor is introduced to improve the Q value of the resonant cavity.Finally,the output frequency tuning range of the VCO is 23GHz-26 GHz,the phase noise range at the 1MHz frequency offset is-98.143 d Bc/Hz-103.078 d Bc/Hz,and the circuit power consumption is 4.19 m W.2)High-speed millimeter-wave divider link.It consists of injection-locked frequency divider,two-stage CML frequency divider and programmable frequency divider.The factors affecting the locking range of the injection-locked frequency divider are analyzed.The dual-injection structure is used.Differential signals are injected from the tail current source and the cavity directly.The injection-locked frequency divider achieves a wide lock range of 21-29 GHz.The power consumption is 4.9m W.3)Low mismatch charge pump and phase detector with no dead band.The non-ideal factors of PFD and CP are analyzed in detail.The anti-dead-time pulse generated by the delay module is added to eliminate the dead-time of PFD.The complementary switch,error amplifier and unity gain buffer are used to reduce the CP current mismatch and Charge sharing and other issues.The cascade simulation logic of PFD and CP is correct.The phase detection range of PFD is [-356,356].The mismatch current of CP is less than 0.5% in the range of 0.15-0.9V output voltage,and the absolute value of the current is less than 1.5%.The current noise at the loop bandwidth is-236.593 dB.Based on the above modules,a 24 GHz millimeter wave phase locked loop was designed using SMIC 55 nm 1P6M CMOS process,including LC-VCO,frequency divider link,PFD and CP modules and filter modules.Layout area size is 1.1mm * 0.65 mm.Post-simulation results show that the output frequency range of the PLL is 23.2GHz-25.6GHz,at the output frequency of 24 GHz,the phase noise is-96.74 d Bc/Hz@1MHz,the lock time is less than 5us,and the power consumption is 14.6m W at 1.2V.The millimeter wave phase-locked loop has certain advantages in power consumption and lock time in the same type of PLL.