CMOS High-speed Adjustable Frequency Phase-locked Loop Design

With the rapid development of CMOS technology,the development speed of PLL technology is also very fast.From micrometer technology to sub-micron technology to deep sub-micron technology,the integration of chips has been greatly improved,and the working frequency of the system has been greatly improved.At the same time,PLL must integrate with some high-speed communication modules,such as high-speed digital logic circuit,analog IC and so on,on the same semiconductor chip,which requires PLL to work in a high frequency environment.Therefore,the design of high-performance phase-locked loop circuit is of great significance for the development of today's society,which is also a key and difficult point in today's integrated circuit design.This paper is based on the Cadence platform,using CSMC 0.18?m CMOS technology,designing a high-speed tunable PLL frequency synthesizer.Using the Cadence software platform,the circuit is designed and simulated,and a small chip area frequency-division phase-locked loop is completed.The overall simulation results show that:when the power supply voltage is 1.8V,the input reference signal is a 100MHz square wave signal,the output frequency of the phase-locked loop can reach 1GHz,at the same time,in order to meet the requirements of wireless data transmission,broadcasting news intercom and other fields,the PLL clock outputs the frequency signal of 500MHz,333MHz,250MHz and 200MHz through the frequency divider unit and the duty ratio of the output clock is within 45~55%.The lock time of the PLL is less than 10?s.The overall layout area is approximately 0.046mm~2 and passes the DRC and LVS verification.The adjustable frequency locked loop can be applied in the radar system,frequency hopping communication,electronic measurement and confrontation,broadcast television and other fields;as a novel device in a wireless communication system receiver,it has important engineering value and broad market prospects.