The Research Of Key Technique For 5GHz Low Spurs Charge Pump Phase-locked Loop

With the rapid development of communication technology,the use of the fifth generation mobile networks(5G)is been gradually extended from commercial communication to its civil counterpart,which is driving the world into an era of faster and more convenient communicating generation.5G technology mainly uses high-frequency carrier blow 6 GHz or millimeter wave above 24 GHz for communication.It aims to realize that human beings are able to get in touch with the world immediately at any moment in any corner of the earth.In the radio frequency transceiver technology,the frequency synthesizer is one of the core modules of the RF front-end circuit that implements the functionality of adjusting the oscillator quickly to generate high-purity,high precision RF signal by the feedback system and lock the phase of signal.Obviously,its performance has a crucial direct influence on the performance of the frequency transceiver system.Higher speed,higher resolution ratio,lower power consumption,lower spurs,etc.,such these technical indicators have been the key to the design of frequency synthesizer,which leads the development of frequency synthesizer technology.In the paper,the basic system architecture of phase locked loop(PLL)frequency synthesizer is briefly summarized,and the vital loop parameters of PLL are given and analyzed carefully.Then,based on the assumption of continuous system,the linear transmission model of the loop is established,and the noise transmission characteristics of the loop are described detailedly.Secondly,according to the idea of designing from the system level to the module level,this paper proposes the dual-path PLL architecture with proportional path and integral path.The noise performance of the proposed circuit construction is compared with its traditional counterpart.Based on the necessity of fast calibration time for better phase noise and spurious performance in the dual-path PLL architecture,a dual-path PLL architecture with fast calibration mechanism is designed,and then detailed exposition of the working principle of the new construction is given.Next,each sub module of PLL are analyzed in depth,and the designing of some is optimized.Based on the proposed dual-path PLL architecture,a current Calibrating charge pump(CP)and a double-tuned voltage controlled oscillator(VCO)are designed.Finally,based on TSMC 65 nm CMOS process,a low spurious CP PLL frequency synthesizer with 4.9-7.5GHz locking range is designed.When the chip has been taped,the output spectrum is tested by the spectrum analyzer Agilent N9030 A.The result shows that the reference spur of the output spectrum is-67.33 d B without calibration with the output frequency of 5.47 GHz and reference frequency of 42.72 MHz,while in the calibration mode,the reference spur is-73.04 d B.In other word,the calibration system improve the spur performance of the PLL for a decrease of 5.71 d B.Besides,the in-band phase noise is-107 d Bc/Hz at 1 MHz offset from the carrier,and the integrated jitter in 1k Hz-10 MHz is 399 fs.