Research On FPGA Design And Key Circuit Radiation Reinforcement Method

SRAM-based field programmable gate arrays (FPGAs) are a popular option for communications, commercial electronics, defense and military or space-based applications because of their flexibility, re-programmability, and low application development costs. When used for defense and military or space, they are sensitive to radiation environment due to single event upsets (SEU) on configuration bits caused by high ions. Meanwhile these upsets also happen in DFF. Consequentially, the function of FPGA will be changed with all of these errors. With the development of CMOS technology, device size and the space between sensitive nodes are smaller, multiple SRAM cell upsets, caused by single event, become importance failure modes. Today, considering of the performance and cost, the traditional hardened technique show its insufficiency more and more obviously. With all these situations mentioned above, on the basis of independent design of FPGA’s key circuit, we analyze the specific effects, caused by radiation environment, on SRAM-based FPGA and propose effective solutions to solve the SEU problems.The main works and contributions of this dissertation are as follows.FPGA logic functions are realized mainly by Configurable Logic Blocks and Programmable Routings, which are key modules in FPGAs. The CLB structure is described in detail and the programmable routing for embedded IP cores is designed and implemented in this paper. Moreover, the influences which will affect FPGAs from SEUs are analyzed. Besides more function circuits added, the volume of CLB is also2times sufficient than the traditional LUT combined with DFF structure. The programmable routing is composed of global routing and module routing. The GRM part of module routing is uniform, which makes it more convenient for array extension and IP cores insertion. The FPGA function errors caused by SEU include: functional errors in LUT, connection errors between routing resources, short errors and DFF upsets.Considering the upsets of configurable bits and DFF, novel SEU hardened SRAM and DFF is proposed for SRAM based FPGA. It extends the conventional6T SRAM structure by connecting a memristor between the PMOS and NMOS transistor which compose cross-coupled invertors. The high resistance state of memristors is used in this cell. Compared to other SEU hardened cells like HIT, DICE and10T cell, its area is reduced by60.7%、45%and63.3%respectively with similar LET threshold. The SEU hardened DFF combines the hardened technique of Muler C and the SRAM harened method mentioned above. In addition to SEU-tolerance, it can also filters SET from combinational logic.Aiming at MBU of SRAM, novel MNU hardened SRAM cell is proposed for SRAM based FPGAs. It extends the conventional6T SRAM structure by connecting memristors between the information nodes and drains of the transistors which compose cross-coupled invertors. With memristors connected to drains of OFF transistors configured to high resistance state while others configured to low resistance state. The structure forms stable voltage divided paths, which makes this cell immune to multiple-node upsets. Furthermore, the MNU-hardened SRAM cell has nonvolatile ability, which means its information will not be lost after being powered off Since memristors should be configured to correct state in write opration. We re-defined time sequence of write operation.Moreover, An MNU cell array is designed for test. Compared to conventional SRAM arrays, new circuits, such as the memristor configuration circuit and the bit line data generation circuit are designed to configure the state of memristors.