Design And Implementation Of A High Performance Pipelined ADC For High Speed Silicon Microstrip Detector Readout Circuit

The continuous innovation of semiconductor technology has promoted the rapid development of semiconductor detectors.Among them,Silicon Microstrip Detector has become a key research object with its excellent position resolution(1.4?m),and is widely used in medicine,industrial and high-energy physics laboratories.The main components of the readout circuit are a front-end analog signal detection module,a analog to digital unit,and a digital signal processing unit.Analog Digital Converter plays an important role in the data readout circuit.Its function is to quantize the analog signal into a digital signal.The accuracy of the detector is depended on the performance of ADC.This work is based on the background of 1×128 array silicon microstrip detectors with the frame rate of 1MHz.And the readout circuit uses 64 columns to shares one converter.This subject researched and designed a pipeline analog-to-digital converter,which is used in column-level readout circuits to meet the system's requirements of high-speed,high accuracy and low power dissipation.First,this article describes the principle of the pipeline ADC.And next,analyzes several typical errors in the pipeline architecture in details.Based on this,a 12-bit Pipeline ADC with the sampling rate of 80 Msps is designed.The front-end sample-and-hold circuit uses a capacitor flip-around structure to reduce system power consumption and noise.And use an improved bootstrap switch to improve sampling accuracy.The intermediate sub conversion stage uses inter-stage opamp-sharing technology to reduce the number of op-amp to reduce system power consumption.A differential dual-input op-amp shared multiplier digital-to-analog converter is designed.Since the inputs of op-amp are alternately connected to the common voltage for reset,no additional reset clock is needed to eliminate the memory effect.In addition,there are no extra switches used to switch off the op-amp.So,it does not have the parasitic channel formed by the switching parasitic capacitance between the two stages,and the problem of inter-stage crosstalk is also well solved.In order to further reduce power consumption,the reduction ratio of the sampling capacitors of the first sub-conversion stage to the fourth sub-conversion stage is 0.6,and it will not be reduced thereafter.In addition,when the latter stage completes the sampling of the signal and the former stage is still in holding phase,the comparator in the latter stage completes the comparison operation.So that the kickback noise of the comparator will not affect the signal transmission.The design in this work is implemented in a 0.13?m CMOS process,and uses Cadence Spectre software to conduct circuit design and pre-simulation,layout design and post-simulation verification of the pipeline ADC.The designed ADC core module layout area is 2.56 mm × 0.54 mm.After extracting parasitic parameters from the layout,at a sampling frequency of 80 Msps,the frequency of the input sine wave signal is 1.035156 Msps.The simulation results show that the pipeline ADC designed in this paper has a SNR is 66.3d B,a SNDR is 65.9d B,a SFDR is 78.7d B,a THD is-76.1d B,and ENOB is 10.65 bits.The total power dissipation is 290 mW.