Design Of 100Msps High-speed Pipelined ADCs

Pipelined analog-to-digital converters(ADCs)have been widely used in applications such as wireless communication,audio,video,and medical imaging.With the rapid development of electronic information industry,the performance requirements of ADC have been greatly increased.This thesis focuses on the design of 100Msps high-speed Pipelined ADCs.At the beginning of the thesis,the primary architectures of ADC and the fundamental paramaters are introduced.Then from systematic point of view,some low-power design techniques are discussed,and the structre of a 14-bit 100Msps high-speed pipelined ADC is determined.The error factors are analyzed,and thus the calculation of recommended requirements are made,such as the size of sampling capacitors,the gain and bandwidth of opamps.Moreover,a Simulink model is build to verify the correctness of calculation.From the perspect of circuit,detailed design flow of the key blocks are described.The front-end circuit combined the sample-and-hold circuit and the first 2.5bit MDAC by opamp-sharing.An improved dual-input switching operational amplifier with variable transconductance was proposed to meet the different requirements of the sample-and-hold and MDAC,and to eliminate memory effect and crosstalk.A dual-channel bootstrapped sample switch is presented.The bulk modulation effect is reduced and thus the linearity of the sample-and-hold circuit is improved.Simulation result shows SNDR and SFDR of the adopted switch increased 5.2dB and6.3dB,respectively.The influence of kick-back noise on signal transfer is suppressed by timming control.The rest of the pipeline stages consisted of five 1.5bit opamp-sharing stages.The simulation results showed that the ADC achieved a SNR of 83.4dB,a SNDR of 82.3dB,a SFDR of 90.6dB,a THD of-88.6dB,and an ENOB of 13.37 bit,with a sampling rate of 100Ms/s and an input signal frequency of 46MHz.Compared with no variable transconductance,ENOB increased 0.36 bit.DNL and INL were within±0.5LSB and±1LSB respectively.Under a 1.8V supply,the overall power consumption of the ADC was 116 mW.Based on a 0.18?m CMOS process,ADC core occupied an area of1.4mm~2.The post simulation results showed that the ADC achieved a SNR of 82.6dB,a SNDR of 78.7dB,a SFDR of 84.1dB,a THD of-81.0dB,and an ENOB of 12.78 bit,with a sampling rate of 100Ms/s and an input signal frequency of 46MHz.In order to reduce the design difficulties of opamp in 100Msps high-speed pipelined ADC,a statistics-based digital background calibration method is proposed to elimated the first and third-order error of opamp.Based on Simulink model,a 12bit 100Msps high-speed pipelined ADC with opamp first and third order error is calibrated.After calibration,SFDR improves from 59.8dB to 93.9dB,SNDR improves from 50.1dB to73.1dB and ENOB improves from 8.0bit to 11.9bit.Further more,a variable LMS convergence method is presented to tremendously speed up the convergence,the required sampling numbers of ENOB convergence are reduced from 1.8×10~7 points to 1×10~7 points.