Research And Design Of High Speed And High Resolution Pipelined-SAR ADC

With the advent of the Internet of Things era and the development of 5G communication technology,higher performance requirements have been put forward for high-speed and high-resolution analog-to-digital converters(ADCs).Although the conventional pipeline ADC can achieve high speed and high resolution,it requires multiple interstage residue amplifiers,resulting in high power consumption.The successive approximation register ADC has the advantage of high energy efficiency,but its speed is limited by multi-cycle quantization,and its accuracy is limited by comparator's thermal noise and capacitors' mismatch.A hybrid architecture,Pipelined-SAR ADC,combines the advantages of the two,which can achieve high speed and high resolution while achieving high energy efficiency,and has become a research hotspot in this field in recent years.This thesis takes 14-bit 100 MS/s Pipelined-SAR ADC as the research object,and studies the key technology and design method in the high-speed and high-resolution Pipelined-SAR ADC.First,the working principle of Pipelined-SAR ADC is studied,and its various non-ideal factors are analyzed.On this basis,for the 14-bit 100 MS/s performance requirements,two specific structures based on different residue amplifiers are determined,one based on a closed-loop opamp and the other based on an open-loop dynamic amplifier.The former has small gain error but high power consumption;the latter has low power consumption but large gain error.In the design of the residue amplifier,aiming at the problem that it is difficult to design a high-performance opamp under advanced technology,this thesis adopts the gm/Id lookup table methodology to design the opamp and optimize its power consumption,so as to realize the optimal design of high-performance opamp under multi-dimensional specification constraints,and then the dynamic amplifier is analyzed and designed in detail.In addition,other key modules in Pipelined-SAR ADC are studied and designed in this thesis,including capacitor DAC,dynamic comparator,asynchronous logic circuit,etc.Aiming at the offset error and interstage gain error in the ADC,a calibration circuit based on an analog method is adopted,which is characterized by low hardware overhead and can realize the joint calibration of these two errors.In addition,a dither based digital calibration method is also studied to solve the first-stage capacitor mismatch error and the interstage gain error.Based on the SMIC 55 nm CMOS process,the circuit design of two pipelined SAR ADCs based on different residual amplifier structures is carried out in this thesis,and the circuit is simulated and verified using Cadence's Spectre software.Simulation results show that the closed-loop opamp designed based on the gm/Id methodology has a power consumption of 1.44 m W under the performance requirements of the open-loop DC gain of 92 d B,the closed-loop gain of 16,the closed-loop negative 3 d B bandwidth of 180 MHz,and the total output integrated noise of 1.44 m Vrms.When the sampling frequency is 100 MS/s and the input signal frequency is 49.78 MHz,the ENOB of the ADC based on the closed-loop opamp reaches 12.3 bit,meeting the performance requirements.For the ADC based on the open-loop dynamic amplifier,after the analog foreground calibration,the SNDR is increased from 67.83 d B to 76.08 d B,SFDR is increased from 79.17 d B to 90.92 d B,and ENOB is increased from 10.97 bit to 12.34 bit.The total power consumption of the key circuit is only 264.3 u W,which meets the requirement of high energy efficiency for the high-speed and highresolution Pipelined-SAR ADC.