Design Of Pipelined ADC Based On Zero-crossing Detector Under CMOS Process

Analog-to-digital converter(ADC), as the bridge of analog and digital signals, is inevitable in signal processing devices. Pipelined ADC, as can get the best compromise among power consumption, speed and resolution, is widely applied in the fields of image processing, mobile communications, digital high-definition television(HDTV) and fast Ethernet.The scaling of technology and supply, cut areas and power consumptions of digital circuits effectively, but also increased the complexity of analog and mixed signal circuit designing. The bottleneck of traditional structured pipelined ADC is the designing of high gain high bandwidth operational amplifier(op-amp). Power consumption of the op-amp accounts for a large proportion of system power consumption, so very low power efficiency, also signal range of op-amp greatly limited system linearity. Op-amp-less residue amplify circuit has become a hot research topic in pipelined ADC designing.As open-loop amplifying, stable feedback was not in need in zero-crossing detector and current source structure, lower power consumption and wide dynamic range could be achieved,also influence of process and voltage scaling on circuits designing could be released.A 10 bit, 10 MHz pipelined ADC was proposed under GSMC 0.18 um CMOS process with zero-crossing structure.Considering the compromise between power consumption and speed, S/H-less 1.5bit per stage structure was adopted in the system. The whole system was composed of 11 stages, in which the first 10 stages output digital codes and the last stage works as the load. In full-differential structure, in order to reduce single stage offset and supply noise, current source with dummy transistors was used to improve systematic linearity and common mode rejection performance. Zero-crossing detector with pre-amplifying plus buffering structure was adopted to shape output waveforms. Pipelined structure with 1.5 bit per stage and same inter-stage gain, complexity of inter-stage amplifying circuits and digital correction circuits was lowered. Except the ADC core circuits, peripheral circuits such as non-overlapping clock generation circuit, reference voltage and current generating circuits was also completed. The whole layout was designed under GSMC one poly six metals(1P6M) process.Simulation results shows that, under 10 MHz sampling frequency and 1MHz sine wave input, the ADC’s SFDR achieves 66.39 dB, ENOB achieves 8.57 bit, DNL and INL achieves 1.36 LSB and 2.24 LSB respectively, core power consumption of the ADC is 22.5mW. The size of the system layout was 1.887mm×0.743 mm,with peripheral modules inside.