Design Of Low Power14-b100-MS/s Pipelined ADC

Along with popularity of portable electronic devices, power has become a important target of circuit design. As a key module of communication chain, low power design of Analog-to-Digital Converter is a hot research topic. Pipelined ADC has been proved the most suitable architecture for high speed and high resolution ADC. This paper modified the conventional low power design technique. Based on the modified low power technique, this paper deigned a14-bit100-MS/s pipelined ADC in TSMC0.18μm CMOS mixed signal technology.Operational amplifier is the most power hungry module of pipelined ADC. There are some low power techniques for opamp, such as switched opamp technique, double sampling technique, opamp sharing, opamp sharing and capacitor sharing. The drawbacks of opamp sharing are memory effect and the additional switch. The drawbacks of opamp and capacitor sharing are additional zero phase and memory effect. This paper modified the low power technique and eliminated the disadvantages of the conventional opamp and capacitor sharing technique. The ADC merged sample-and-hold circuit (SHC) and the first stage by proposed technique with the rest stages using modified opamp sharing technique.The14-bit100MSPS ADC consists of SMDAC, backend pipelines using opamp sharing, voltage reference and digital calibration. Simulation results show that the ADC achieves signal-to-noise and distortion ratio (SNDR) of77.6dB, spurious free dynamic range (SFDR) of87.3dB, differential nonlinearity (DNL) of±0.4LSB, integral nonlinearity (INL) of+1LSB, figure of merit (FOM) of0.56pJ/conv, power of350mW at3.3V supply.