A 10-bit Low-power SAR ADC Design

At present,the integrated circuit industry in our country is making great progress.As one of the most important directions,analog-to-digital converter's performance often determines the accuracy of signal processing in the whole system.Because physical signals such as temperature,force,sound,light and magnetism in nature are all analog quantities,analog-to-digital converter(ADC)is widely used in various on-chip systems and as a bridge to convert analog signals into digital signals.Low power consumption has been an important research direction in academia and industry,successive approximation analog-to-digital converter(SAR ADC)is a type of ADC,with smaller size,lower power consumption,and is mostly digital circuit,and with the development of CMOS process toward smaller size,the advantages of the SAR ADC are becoming ever more obvious,so it becomes a typical example of low power consumption ADC,and has become a trend.The purpose of this study is to design a very low power SAR ADC.The main modules which are designed in SAR ADC contain digital logic circuit,comparator and digital to analog converter(DAC).The paper analyzes the basic concepts and latest research of these three modules in detail,and then studies the design method of low-power SAR ADC on this basis.Since DAC is the major source of power consumption,this paper analyzes the existing switching modes and innovates on this basis,proposing two switching modes,one can significantly reduce power consumption,and the other has stable common-mode level and small area,and each has its advantages and disadvantages.For the design of the whole successive approximation analog-to-digital converter system,the DAC part of this paper chooses a DAC switching mode which has the most obvious advantages in reducing power consumption,and on this basis,the dynamic latch comparator and simple digital logic are used to complete the design of an ultra-low power SAR ADC system.Under the 80 nm process and 1.8V power supply voltage,a 10-bit low-power approximation ADC with sampling speed of 200 k S/s was designed,the effective bit is 9.72 bit,the power consumption is 780 n W and the quality factor is 4.2 f J/step.