Design Of High-Speed Energy-Efficient Analog-to-Digital Converter

The rapid development of wearable mobile device, infrared sensor and wireless sensor network puts forward higher requirements on the miniaturization of electronic systems, and analog to digital converter (ADC) is the essential part of the system, its performance directly affects the performance of the whole system. Successive approximation register analog to digital converter (SAR ADC) is widely used for a long time for its low power consumption, small size, moderate speed etc, its design technology is getting more and more attention.This paper initially analyzes the common structure and working principle of ADC, and compares their respective advantages and disadvantages. Then, introduced some conventional dynamic comparator and analyzed those working mechanism,meanwhile this paper designed a low power dynamic comparator without pre-amplifier and simulated it. After that, this paper discussed the working principle of digital-to-analog converter (DAC) in SAR ADC analyzed different configuration and compared those power consumption, based on this analysis, merged capacitor switching is selected and used a attenuation capacitor to satisfy low power design. In addition, this paper analyzed several digital control logic, then design a new asynchronous control logic, compared with conventional, this logic used less transistor to achieve low power consumption. Eventually, based on these studies, a 8-bit 35MS/s SAR ADC circuit is designed.By using the Cadence design for circuit design and simulation platform, completes the ADC layout and simulation, the simulation experimental shows that under the power supply voltage of 1.8V, the proposed SAR ADC is 35Msps, and when the input signal frequency is 0.097 MHz, its SNR is 46.0dB, SNDR is 44.8dB, SFDR is 53.9dB and ENOB is 7.15bit, power consumption is 0.65mW, FOM is 132fJ/step.