Design Of SAR A/D Converter In0.13μm CMOS Process

As the interface between analog and digital systems,ADC(Analog to DigitalConvert) is widely used in sensors,audio,video,instrumentation,communications andother fields,which plays an important role in signal processing systems. As informationtechnology continues to evolve, people are increasingly demanding high-performanceADC.Successive Approximation ADC(SAR ADC) is a common structure in A/Dconverts.SAR ADC generally has8～16-bit resolution, less than5Mspssampling-rate.With its mixed advantages in resolution,speed,power size and cost,SARADC is widely used in potable devices,automotive electronic equipment andanalog-to-digital interfaces of micro-processors and so on.A3.3V/1.2V for the voltage resources,12bits for the resolution,16M Hz for theclock frequency and1Msps for the sampling-rate is designed in this thesis.The model isused by SMIC logic013_IO33_v2p8,and its corner is tt.By the pre-simulation for the circuit,the ENOB is11.931593bit,the SFDR is81.088243dB,the SINAD is71.588192dB,the THD is-79.252528dB.By thepost-simulation, the ENOB is10.660062bit,the SFDR is70.392002dB,the SINAD is65.933573dB,the THD is-68.456437dB.The main study work is:First,I design a comparator with a two-stage pre-amplifierand a latch,which could work perfectly by1Msps sampling-rate.Second,I design asegmented capacitance digital-to-analog converter(DAC) with7bits in MSB and5bitsin LSB.I also study the effect of the performance parameters of SAR ADC,when the thecapacitance mismatch.