Fast Back-end Design Based On The Method Of Pre-fetching Clock Information

As the process size decreases and the chip size becomes larger,the complexity of the circuit becomes higher and higher.In order to meet the requirements of chip timing,power consumption and area,the number of iterations increases and the design cycle lengthens.The cycle of the chip design directly determines its competitiveness in the market.Since the clock signal is the most important part in the digital system,the implementation of the clock tree occupies a large proportion of the design cycle,so the chip is accelerated while ensuring the design quality.The speed of design,especially the speed of speeding up the implementation of the clock tree,becomes increasingly important.Based on the design flow of the chip,this paper proposes an acceleration scheme that combines the front-end code to obtain clock information in advance before the physical implementation phase.First,before the clock tree is implemented,constraints are generated quickly and automatically synthesized in accordance with design requirements,and auxiliary information such as clock specifications files and clock structure diagrams are automatically generated based on this.At the same time,the appropriate relationship is automatically determined based on the relationship between the data flows between input and output ports location.Then,in the implementation of the clock tree,an appropriate structure is selected to realize the clock according to the established automatic clock structure model,the number of metal layers that can be used in the design,and the target unit utilization rate.Finally,after the clock tree is implemented,combined with the determined clock structure,the analysis of the timing library and timing report can automatically generate commands that can be directly used by the tool to repair timing violations.Among them,the repair of using useful skew principle is particularly important.Through the realization of the pipelineless processor,it is shown that the fast design method can automatically complete multiple steps in the physical implementation process,such as automatically generating logical synthesis constraints,clock structure diagrams,placing port command,etc.And using both the fast design method and the traditional design method implementing other test examples,the results also show that the fast design method can exchange routing resources for timing convergence by implementing different clock structures when routing resources are sufficient.Among them,in the implementation process of dual-issue processors,the fast design method has achieved a clock grid structure.Compared with the fast design method,the clock line length has increased by 1.13 times,and the number of timing violation paths has been reduced to 36%.In the implementation process,the fast design method realized the H clock tree structure,the clock line length was increased by 0.4 times,and the number of timing violation paths was reduced to 56%.