Design Of Digital Interface Circuit In ?-?ADC And Research Of Backend Implementation

The role of Analog to Digital Converters and the development status of ?-?ADC are introduced,which explains the significance of this topic.Firstly,put forward a new design flow of digital interface circuit in ?-?ADC which based on the general flow of ASIC has been proposed.Then,with the understanding of SPI protocol and the division of chip module,the design scheme is determined,and the RTL code and functional verification are completed,and Synopsys' EDA tools are used to complete the back-end implementation of the overall digital circuit.Firstly,the front-end design for the clock,reset,and bus interface modules of the digital interface circuit in the ?-?ADC are completed.The difficulty of the clock system design is that the clock phase switching must be designed without glitches,and the key point is the design of the low-power divider.The challenge of the reset system lies in the design of the digital power-on reset module.The bus interface module refers to the Motorola SPI bus protocol,and working in the slave mode.The key point of bus interface module is to synchronize the asynchronous clock domain between the master clock MCLK and the serial clock SCK,as well as the processing mechanism of the output data of the analog-to-digital converter.Then,the RTL code of the digital interface circuit is completed using the Verilog HDL,and the pre-simulation verification and analysis are completed using the Modelsim tool.The results show that,the design of digital interface circuit was successfully.Lastly,the back-end implementation of a whole digital IC in a ?-?ADC is accomplished based on the CSMC 0.35 ?m CMOS process.Firstly,the logic synthesis is completed adopting the innovation which is a new scheme of combining the asynchronous frequency division and clock gating technology.Compared with the traditional scheme,the power consumption is reduced by 27.68%and the area is reduced by 1.82%.Then,the logic equivalence checking is applied to the synthesized gate-level netlist and the RTL code,which the result shows that their function are consistent.Then,the placement and route are completed using the ICC tools,and the clock tree synthesis is completed adopting the proposed innovation which is a new scheme of combining the decrease of clock tree series and increase of hold time margin,which obtained the better quality of result,and the hold total negative slack is reduced by 95.62%.When the parasitic parameters are extracted and the static timing analysis is completed,which result shows that the number of buffers required for timing closure is reduced by approximately 98.13%,and the running time is reduced by 97.25%,and the wiring congestion level is effectively reduced,and the timing closure is quickly and effectively achieved.Then,the physical verification is passed which include the DRC and LVS verification.Then,the post-simulation verification is also passed,which indicated their function is consistent between routed gate-level netlist and RTL code.Then,the power analysis is compeled,and the final chip area is 2583 x2576p?m2,less than 3000×3000p?m2;the maximum average power consumption is 2.78mW,less than 3mW,all meet the design requirements.