Research On Clock Tree Synthesis Optimization Of The ASIC Backend Design

In this paper, optimized clock tree synthesis method on backend physical layout design for one Digital Signal Process chip ADP32, which is controlled by IOT, is proposed. Experimental data show that the method can effectively simplify the clock tree structure and reduce the area and power consumption of the clock tree.Currently, the chip has successfully entered into the phase of flow sheet.The clock signal is the benchmark for normal work of the circuit, and also a signal of the longest attachment, highest turnover rate, as well as peak load of the electrical systems. Clock signal must be guaranteed that key timing sequence can work normally, even under the worst environment, otherwise it will lead to temporal disorders. As the crucial step for entire back-end design, the clock tree synthesis optimization of ASIC backend physical design is to convert the integrated front-end ideal clock signal to actual signal wires. Clock tree synthesis aims at minimizing the clock delay and skew, maximizing timing convergence chances, as well as minimize the number and area of clock buffering, reducing power consumption. In a word,the performance of the clock tree directly affects the entire chip area, power consumption and congestion rates.Clock tree synthesis optimization research will be done on the basis of SOCClock tree synthesis optimization research will be done on the basis of SOC Encounter platform of the Cadence P&R tools in this paper, combined with ADP32 chip backend physical design process. Firstly, the basic process of the back-end design will be introduced, with its content in all stages of the process and announcements attached. Then, the basic principle and clock network classification,related to the research subject of this thesis, will be detailed. Finally, Solutions are proposed by the careful analysis of clock tree structure design and problems in real projects. Furthermore, a low power consumption and small area clock tree method will be proposed, by setting and optimizing the three parameters-Buffer,Global Excluded Pin and Leaf Pin Group-of the guidance documents, on the premise of timing convergence.The experimental results show that power of clock tree are improved by3.6% and the total chip’s area are reduced by 0.4% respectively with the rational sets of the three kinds of parameters, compared to the traditional clock tree synthesis method.