Improvement And Design Of LDPC Decoding Algorithm On FPGA

In this era of rapid development of information technology,the world is being changed by information,and our lives are changing.This requires a higher speed,more efficient and more reliable way of transmitting information.Therefore,it is especially important to choose a coding and decoding technology with good error correction performance.Therefore,the Low Density Parity Check Code(LDPC)is studied,which has the advantage of being close to the Shannon limit.LDPC codes have a very wide range of applications.Recently,in the coding war of the 5G protocol,the LDPC code defeated the Polar code and the Turbo code,and successfully won the 5G medium long code coding scheme.In this paper,the decoding algorithms are studied.In the research process,it is found that the most commonly used are the minimum sum decoding algorithm and the normalized minimum sum decoding algorithm.Although it reduces the complexity of the implementation,it loses performance.The extent of compensation is still to be improved.Secondly,an improved normalized minimum sum decoding algorithm is proposed.The improved algorithm is simulated and analyzed by the code length and code rate.and it is found to be consistent with the classical decoding algorithm.According to this,the algorithm is simulated and analyzed by the compensation factor,and the superior value is determined.A similar idea is proposed to improve the minimum sum decoding algorithm with offset.The simulation analysis of the factors such as code length and code rate is also carried out.It is found that the improved algorithm is consistent with the performance of the classical decoding algorithm,and it is simulated and analyzed by the compensation factor to determine the superior value.On this basis,the improved algorithm and the classical algorithm are simulated and compared under the same conditions.It is found that when the SNR is greater than 1.5dB,the performance of the improved algorithm is significantly improved,and the improved normalized minimum sum decoding algorithm is better.Comparing the computational complexity,the improved algorithm is at the same level as the normalized minimum sum decoding algorithm,it just increases the number of calculations in its comparison operation,and this is perfectly acceptable.Finally,according to the coding and decoding scheme determined above,the design of each module of the encoder is completed,including serial-to-parallel conversion,coding,control,and storage modules and so on.The simulation verification of the encoder is completed,which proves the correctness of the design.Next,the module design of the decoder is completed,including the design of control,buffer,storage,variable nodes,check nodes and other modules.The decoder is simulated and verified,which proves the correctness of the decoding module design.Finally,the performance of the coding and decoding module was verified by using the established communication system.The final measured performance curve was compared and found to meet the design requirements.