The Decoding Research And Hardware Implementation Of LDPC Codes Based On FPGA

The linear block code is called a binary low-density parity-check code if it is based on a sparse parity-check matrix. The discovery of the LDPC codes is a great progress after the turbo codes in the area of Error-Correcting Codes. The LDPC codes are relatively easy defined and can outperform the turbo codes with sufficiently long block lengths. Its decoding complexity is also lower than turbo code. Many telecommunication organizations and companies will have LDPC to be the Error-Correcting scheme of the fourth generation mobile communications standard. Recently, LDPC code has drawn the worldwide attentions in channel coding community.Based on the systematic analysis research and study of the LDPC codes, this paper firstly describes the encoding of the codes in algorithm and frame the hardware decoder based on two element algorithms. And we realize the bottom elements of the hardware encoder too. Then, we analyze the Belief Propagation (BP) algorithm and the Log-BP algorithm and simulate the Log-BP algorithm which is suitable for the implementation of the hardware decoder. The simulation results show Log-BP algorithm can be the algorithm of hardware implemention and its performance satisfies the design requirements.Then, the author analyses how to choose a better data quantification in the hardware implementation in order to find a better tradeoff between the design performance and used-area. Based on the theory, we use the idea of top-down design to program the decoder with Verilog Hardware Description Language. Moreover, we synthesize and analyze the static time of the design with Synplify Pro and QuartusII to verify the correctness. The simulation results show the precept of using FPGA to be the platform the hardware implementation is feasible. Finally, in accordance with the the high-rate and long-code LDPC code, we optimize the structure of the modules and show the prospects of adaptive decoder.