DVB-S2 Standards Before The Realization Of Forward Error Correction Code Encoding And Decoding Research And FPGA

Low density parity check(LDPC) is also called Gallager code, it is a kind of linear block codes with sparse parity matrix and it was put forward by Gallager in1962,but it had not been developed due to the constraints of hardware implementation then,while MacKay and Neal rediscovered LDPC codes with iterative decoding had the performance near Shannon limit in1995. LDPC code is a kind of hot channel coding technology,which developes quickly in recent years and it is mainly used in some future applications,such as4G、optical fiber communications and aeronautical communications.LDPC codes can be decoded in parallel, its hardware implementation is low complexity,and its design method is also very mature, which not only overcomes the problem of long code cannot be decoded, and the performance is close to the maximum likelihood decoding. Forward error correction coding scheme(FEC) of DVB-S2adoptes the BCH code as the outer code andLDPC code as the error correction coding methods, The scheme solves the problem of high complexity of longer codes,the performance can also perform well at low SNR. Studying the efficient encoding and decoding algorithm of the error correcting code and the high efficiency and low cost of hardware design is a meaningful work.Low complexity encoding and decoding algorithms and hardware structure suitable for practical application have been mainly studied In this paper based on in-depth analysis of the DVB-S2standard in this paper.Firstly, The definition and construction methods of LDPC are presented in this paper, and the characteristics of the DVB-S2BCH code are then introduced, DVB-S2LDPC code is mainly discussed.Secondly, the BCH serial encoding algorithm is introduced in detail in this paper and is simulated using Matlab tool, LDPC code are then encoded with the Low complexity cyclic code encoding method, the problem of data overflow is overcomed in this process. The coding algorithm complexity is also verified from the aspects of the coding bit rate and the space of storage. Once again, several kinds of hard decision and soft-decision decoding algorithms are analized and compared, Fixed-point, quantizing and methods of optimizing the decoder parameters are introduced in decoding in order to improve the hardware complexity, and a simulation analysis is carried out with the aid of Matlab tools.Finally, BCH coding and LDPC encoding and decoding hardware implementation structures are proposed, Verilog HDL hardware description language is used to achieve the FPGA design for encoder and decoder with the help of QuartusII9.1development platform and the Modelsim simulation tools. The simulation results and resource usage are obtained and are also compared with the Matlab software simulation results, the maximum frequency of encoder designed in this paper can reach more than100M and that of decoder can reach more than200M,but the resource utilization is low.