Research And FPGA Implementation Of Non-binary LDPC Code Decoding Algorithm Based On Short Code

In the wireless communication systems,the information bits will be interfered by channel noise during the transmission,so it is necessary to adopt the channel coding technology to reduce the interference.Low density parity check(LDPC)code is a kind of channel coding technology,which has strong anti-interference ability.The non-binary LDPC(NB-LDPC)code is an extension of the LDPC code,which has stronger antiinterference ability and can efficiently transmit information bits.This thesis combines the theory and simulation to research and improve the NB-LDPC code,and completes the corresponding hardware design and implementation.This thesis first studies the definition and characteristics of NB-LDPC code on the basis of finite field.Then the construction method and coding method of NB-LDPC code are comprehensively deduced,and the advantages and disadvantages of different construction methods and coding are analyzed.In terms of decoding,this thesis has further researched and improved the EMS decoding algorithm.The algorithm proposed in this thesis optimizes extended min-sum(EMS)decoding performance from two aspects.Firstly,the adaptive rules are used in the decoding algorithm to shorten the effective length of the message in the iteration,thereby reducing the complexity of decoding.Secondly,weighting factor is used in the iterative process of variable nodes to improve performance.In the proposed algorithm,adaptive rules are added in the decoding process to effectively reduce the average length of the valid messages,thus reducing the complexity decoding.In addition,weighting factor is added in the update iteration process of variable nodes.By this way,the oscillating variable nodes can be corrected by the information of other variable nodes,so as to improve the decoding performance.Through simulation and detailed analysis,it is found that the proposed algorithm is superior to the EMS algorithm in terms of decoding performance and complexity.After a comprehensive analysis of the EMS decoding algorithm,the hardware decoder of the NB-LDPC code is designed and implemented in this thesis.Based on the Quartus II 13.0 platform,verilog hardware description language(HDL)is used to implement the different decoder modules,this including the initialization module,control module and variable node update module.Then,function and timing of the designed decoder are simulated by calling Modem Sim,and resources consumption of the proposed decoder are analyzed.Compared with the EMS algorithm,the proposed algorithm reduces the consumption of logic resources and registers by 19.2% and 13.1%.Finally,the power consumption of the designed decoder is measured and analyzed at different frequencies in this thesis,using the power consumption test software.The result indicates that the power consumption of the designed decoder is lower than the standard EMS decoder at different frequencies.