Ieee802.16 E Standard Ldpc Code Decoder Design And Fpga Implementation

Low-Density Parity-Check (LDPC) codes are linear block codesdefined by sparse parity-check matrix which have been received muchattention in the research areas of channel coding. They have beenattracting much attention in current and future digitial communicationsystems due to their Shannon limit-approaching performance andimplementary potential of high speed encoding and decoding. Thisthesis is based on the application of IEEE802.16e standard. Firstly, wehave made some research on the encoding and decoding algorithmsof LDPC codes, then we have designed and implemented the LDPCencoder and decoder which are corresponding to the IEEE802.16estandard.The major work of this paper can be summarized as follows.1. We have choosed the high speed iterative encoding algorithmas the hardware implementation algorithm by the way of comparingand analyzing all kinds of encoding algorithms. Firstly, we havedesigned the implementary method for the encoder based on theselective encoding algorithm. According to the implementary method,we have designed an efficient overall architecture of encoder, thearchitecture is flexible for supporting multiple LDPC codes of variouscode rates and code lengths. According to the encoder structure, wehave designed all the sub-modules and the optimized memory whichcause to low down the required memory space. The simulation andsynthesis results show that the function of the proposed encoder is rightand the encoder has low complexity and high throughput.2. The TPMP and TDMP decoding algorithms which are based onthe difference message passing have been researched. A modifiedTPMP decoding algorithm has been proposed based on the research ofthe TPMP decoding algorthim combined with the simplified Turbo decoding algorithm.The performace of the proposed TPMP decodingalgorithm is very closed to the BP decoding algorthm while thecomputation complexity is lower. Moreover, a mdodified TDMPdecoding algorithm has been proposed based on the research of theTDMP decoding algorithm combined with the Offset Min-Sum algorithm.The performance loss of the proposed algorithmcan be ignored compared with the BP decoding algorithm whileachieves a lower computation complexity and the offset parametercan be self-adaptation to the channel environment in some degree.Finally, the decoding algorithms have been simulated with Matlab andthe simulation results of the float and fixed decoding algorithms havebeen displayed for various of decoding algorithms. Moreover, thesimulation results have been compared and analysed.3. We have choosed the modified TDMP decoding algorithm as thehardware implementation algorithm. We have designed theimplementary method for the decoder based on the selectivedecoding algorithm. According to the implementary method, we havedesigned an efficient quantizing scheme and the overall architectureof decoder, the architecture is flexible for supporting multiple LDPCcodes of various code rates and code lengths. According to thedecoder structure, we have designed all the sub-modules and thetechnique of memory efficient, configurable early stopping criterion,overlapping of check node and variable node update and dual-pathdecoding for the LDPC code length not more than1152have beenadopted to improve the throughput and hardware resource utilizationof decoder. The simulation and synthesis results show that the functionof the proposed decoder is right and the decoder has low complexityand high throughput.