Research And Implementation On LDPC Encoding And Decoding Algorithms For CCSDS Telecommand Applications

Low density parity check(LDPC)codes,with long block length showing an excellent performance close to Shannon’s performance limit,have been widely used in communication systems,such as wireless local area networks(WLAN)and fifth generation mobile networks(5G).Three LDPC codes with short block length has been proposed by the consultative committee for space data systems(CCSDS),due to the relatively short frame length required in aero space remote control applications.Hence,in the dissertation,the encoding and decoding algorithms for the short block length LDPC codes are focused on.The mainly contents are as follows:(1)In oder to improve the throughput of the quasi-cyclic LDPC encoder,the low-parallel coding scheme is proposed,based on feedback shift register for quasi-cyclic LDPC codes.The traditional quasi-cyclic LDPC coding scheme,based on cyclic shift registers,has simple structure and low throughput;the proposed coding scheme,however,can reach double throughput with the similar resource consumptions,compared with the traditional coding schemes.(2)An improved decoding algorithm is proposed,since short cycles of the short-block-length LDPC codes presented by CCSDS degrades performance of LDPC codes if the standard belief propagation(BP)decoding algorithm is used.The proposed decoding algorithm is based on normalized log-likelihood ratio BP(LLR BP)and uniformly most powerful BP(UMP BP)decoding algorithms,which can achieve better performance than BP decoding algorithm by modifying the process of the check nodes and the variable nodes at the same time.The simulation results show that the proposed algorithm has better decoding performance than the BP and UMP BP algorithms.Moreover,although the complexity of the proposed decoding algorithm is similar to that of the UMP BP decoding algorithm,its resource consumption is much smaller than the standard BP decoding algorithm.(3)The decoding scheme for the short-block-length LDPC codes presented by CCSDS is designed,and a 12 bits decoder of the proposed decoding algorithms is also implemented on FPGA platform by using Verilog HDL,which involves the variable node processing unit,the check node processing unit and the control unit.An automatic test system including on-line monitoring system is completed,and the test results show that the performance of the decoder matches well with the simulation results of the proposed decoding algorithm,which verifies the proposed decoding algorithm has significantly good feasibility and practicability.