Research On Binary LDPC Code Decoding Algorithm Based On MRF And FPGA Implementation

Low Density Parity Check Code(LDPC) is a kind of linear block code. It has an error performance which is close to Shannon limits. Compared with other decoding algorithm, it has low decoding complexity and flexible structure. So it becomes the hot research spot. In recent years, the encoding algorithm and decoding algorithm of LDPC codes have been improved and enhanced unceasingly. And it is widely used in deep space communications, optical fiber communication, mobile communication and underwater, etcFor decoding algorithm of LDPC codes, we bring up that it can be combined with the Markov Random Field. And it can realize the source parameter estimation. At the same time it can use residual redundancy information to improve the error correction ability when it decodes. So it will improve the decoding performance of LDPC codesIn this thesis, the main research sections are describled as follows.First of all, under the condition of analysing the structure of digital communication system and LDPC codes, we will analyse the three representations of LDPC codes which are matrix structure method, several encoding algorithm and decoding algorithm. And we will focuses on the decoding algorithm.The second one, we will analyse the theory knowledge of Markov Random Field, which includes Markov chain of random, parameter estimation, Markov Random Field model and so on. On the basis of analysing Markov Random Field,we will propose LDPC decoding algorithm based on MRF. We will apply Markov Random Field to LDPC code decoding algorithm. It will realize the source parameter estimation, and it can use residual redundancy information to improve error correction ability when it decodes. Then we will use the MATLAB simulation to compare it with other performance of the decoding algorithms.The third one, we will make use of FPGA to design the hardware decoder based on LDPC decoding algorithm. We will use the partial parallel decoder structure and Verilog language to write each decoder module. And we will use the Modelsim simulation tools to get timing simulation diagram of each module. In the end, we will verify the correctness of the design, according to the simulation results and the analysis of the consumption of resources.Finally, we will summarize the research achievements of this thesis and look to the future development direction.