Decoding Algorithm Improvement And FPGA Implementation Of Short Packet Based LDPC Code

In the communication systems,information transmitted on the channel will be subject to interference,which will cause bits errors.Therefore,the effective techniques must be adopted to enhance the ability of the information to resist various interferences during information transmission.Forward error correction code is an effective way to improve the reliability of communication systems,which has been researched in many articles.Low-Density Parity-Check(LDPC)code is a popular technology of channel coding in recent years,whose performance is close to the Shannon limit and has been widely used in communication systems.This thesis takes the LDPC code with short packet as the main research object.First of all,some concepts and basic knowledge of LDPC code are depicted,such as linear block codes,generation matrices,check matrices,and Tanner graphs.Then,the check matrix construction algorithms of LDPC code are presented simply,including Gallager construction,Mackay construction,Progressive Edge Growth(PEG)construction,and quasi-cyclic construction algorithms.Finally,the encoding algorithms based on the gaussian elimination,the lower upper decomposition and approximate lower triangle are studied in detail.In terms of decoding,the principle of hard decision decoding algorithm is briefly described in this thesis.And several soft decision decoding algorithms are studied respectively,including the belief propagation decoding algorithm,the log-likelihood ratio decoding algorithm,the minimum sum decoding algorithm,the normalized minimum sum decoding algorithm,the offset minimum sum decoding algorithm,and normalized belief propagation decoding algorithm.The belief propagation and the log-likelihood ratio decoding algorithms have better performance than other decoding algorithms,while the minimum sum decoding algorithm performs worst.In order to further optimize the decoding algorithm,a modified normalized belief propagation decoding algorithm is proposed in this thesis.The basic principle is that the size of the log-likelihood ratio reflects the size of the probability,and the information reliability varies with different probability.In the process of iterative decoding,reliable information can not only improve decoding performance,but also accelerate convergence and reduce decoding delay,so the impact of this information on decoding should be strengthened.At the same time,for unreliable information,it is necessary to minimize its impact on iterative decoding.Therefore,according to the above properties,the modified normalized belief propagation decoding algorithm sets two thresholds for the information values,and multiplies a gain factor or suppression factor for the information values that meets different requirements.The results show that modified normalized belief propagation decoding algorithm is superior to the normalized belief propagation decoding algorithm,and the performance is almost the same as that of log-likelihood ratio decoding algorithm.Furthermore,the bit error rate simulation and analysis of LDPC code are performed for different decoding algorithms,packet lengths,iterations,check matrixs and code rates.After analyzing the performance of various decoding algorithms,this thesis focuses on the hardware design of the modified normalized belief propagation decoding algorithm.The decoder is divided into different functional modules,and the Verilog Hardware Description Language(HDL)is used in the Quartus II software to implement the programming of each module,which mainly includes initialization information module,check nodes updation module,variable nodes updation module,decision module,and control module.Finally,this thesis analyzes the hardware resources of the minimum sum decoding algorithm,the normalized belief propagation decoding algorithm and the modified normalized belief propagation decoding algorithm,and use the PowerPlay Early Power Estimator to complete the power dissipation testing of three algorithms.