Research And Design Of LDPC Encoding And Decoding Based On FPGA

With the development of 5G and satellite communication technology,low-density paritycheck(LDPC)code has been paid more and more attention because of its low bit error rate.In this paper,the(8176,7154)LDPC code proposed by the Consultative Committee for space data system(CCSDS)for near-earth space communication is taken as the object to study the encoding and decoding algorithm performance of LDPC code,and the algorithm with excellent performance and low computational complexity is selected to complete the hardware design of LDPC encoder and decoder.This paper first studies the basic theory of LDPC codes,including the concept of LDPC codes,construction,and commonly used encoding and decoding algorithms.Then,the encoding and decoding simulation model is designed on MATLAB,and the performance of(8176,7154)LDPC code is studied.According to the quasi-cyclic characteristic of the generator matrix of the LDPC code,the encoding process adopts the algorithm designed by using the generator matrix,uses the cyclic shift register to realize the storage of the generator matrix,and designs the core logic circuit of the encoding algorithm.In the decoding process,the BER of several different algorithms is calculated by simulation,and then the Normalized Min-Sum(NMS)algorithm with superior performance and lower complexity is selected by combining with the complexity analysis and comparison of hardware implementation.Then,because of the uncertainty of scale factor in the formula of message processing algorithm,combined with the quantization scheme used in hardware implementation,a modified algorithm design is proposed to select different scale factors to participate in the operation with the change of decoding iterations.The simulation results under different SNR show that the NMS decoding algorithm with variable scaling factor has better decoding performance.Then the logic circuit design for processing the verification and variable node information in the improved NMS algorithm is completed.After the logic circuit is designed according to the selected algorithm,the hardware implementation of the LDPC encoder and decoder is completed on FPGA.To improve the speed of the encoder and decoder,the parallel data processing design is included in the implementation scheme.The simulation tool in Vivado software is used for software simulation.Under the working clock of 200 MHz,the throughput of the encoder is close to 80 Mbps,while that of the decoder is 2.5Mbps.Finally,based on the AX7020 development version and Microsoft Visual Basic 6.0 software,the upper computer is designed to build a joint test system.The test results under different SNR show that the function of the codec is normal.The LDPC encoder and decoder designed in this paper have the characteristics of simple algorithm design and can complete the normal encoding and decoding work.It has a certain reference value for the research of other LDPC codes.