Research On LDPC Encoding And Decoding Algorithms In Satellite Communication And Its Design Implementation

In recent years, low-density parity-check(LDPC) code has aroused widely attention from scholars in the field of channel coding, owning to the error correction performance of closing to Shannon limit. The research direction of LDPC codes is to reduce the complexity of the encoding and decoding as far as possible, and find the code pattern which is suitable for hardware implementation. Quasi-cyclic LDPC(QC-LDPC) code is a kind of code derived from LDPC code. Using the quasi-cyclic characteristic of check matrix, the encoding of linear complexity can be realized through circulating shift register and the handling capacity can be improved through parallel processing. Relying on the civil space projects and using the combination of theoretical research and hardware implement, this thesis conducted an in-depth research on the encoding and decoding algorithm of QC-LDPC code and realized FPGA-based hardware design of encoder and decoder.After a brief introduction of the LDPC code definition, mode of construction, coding algorithm and other correlation theories, Serial encoder structure and parallel encoder structure are put forward firstly based on QC-LDPC code generator matrix. Then, hardware implementation and simulation proof are done on the FPGA. At last, a comparative analysis of the consumption of encoder ’s hardware resources and the encoding rate of the encoder is conducted through the consolidated results.This thesis described the Sum-Product Algorithm Principle in detail, improved Sum-Product Algorithm from the perspective of hardware implementation and proposed normalized Min-Sum Algorithm.Through BER performance simulation, the improved algorithm is only0.1d B performance loss than the logarithmic domain Sum-Product Algorithm, while the computational complexity is significantly reduced.The quantitative scheme of normalized Min-Sum Algorithm and fixed-point simulation are researchedBased on the traditional decoder structure and modified normalized Min-Sum Algorithm, QC-LDPC code decoder which saves storage resources is proposed. Circuit design and time sequence simulation are conducted to the decoders’ system modules on the FPGA to verify the reliability of the design. Compared with the traditional decoder, the modified decoder doesn’t require the storage of Variable node information. Checking node information of the same row is stored by using compressed storage mode, which reduces the mass storage of space consumption.With a quasi cyclic LDPC codes(496,248) as an example,we build the overall simulation of decoder.Analyzing the performance of decoder,we find that the decoder occupies less resource.The decoder structure proposed in this paper generally can be applied to most of the QC-LDPC code.