Research And Design Of A Clock And Data Recovery Circuit For High-speed Communication

With the development of modern communication technology continuously,as the key module of data receiver in communication chips,the design of the clock and data recovery circuits are getting more and more important.Nowadays,in some high-speed point-to-point communication networks,the data transmission rate has reached nearly 100 Gbps.In order to ensure the accuracy at such a high transmission rate,the design of high-performance clock data recovery circuits has become one of the bottlenecks for further development.In this thesis,a clock data recovery circuit for high-speed communication is designed.And Huahong Hongli 0.35?m BCD process is selected for tape-out.The clock and data recovery circuit has the characteristics of locking fast,having low jitter and no error locking.The circuit designed in this thesis is based on the structure of charge pump phase-locked loop.A dual-loop structure is adopted in the circuit,which are the PLL loop for fast locking and the CDR loop for clock and data recovery.The frequency of reference clock in the PLL loop is 16MHz~33MHz,and the data transmission rate of the CDR loop is 160Mbps~330Mbps.Its working principle is that the PLL loop works first when the chip is powered on,and the output frequency of the VCO locks to ten times of the reference clock's.Then,a lock detection module will detect this state and output a signal,which can control the circuit to switch to the CDR loop.After that,the clock and data recovery works and outputs a low jitter clock signal.In order to reduce area,the design idea of module sharing is adopted.Three modules of the circuit,the charge pump(CP),the loop filter(LF)and the voltage controlled oscillator(VCO),are shared between two loops in this thesis.The difference is that a phase frequency detector(PFD)is used in the PLL loop to discriminate input reference clock and feedback clock.However,in the CDR loop,a Hogge phase detector is used to sample and recover the input data.In addition,the feedback clock of PLL loop is generated by a frequency divider after the output of VCO,while the output of VCO is directly used as the feedback clock in CDR loop.Before the circuit design,the loop was modeled and simulated by using Simulink to determine the detail parameters of the loop.A Verilog-A model was used in Cadence to simulate with some actual circuits to ensure the stability of the system.When we design the circuit,the charge pump and the voltage-controlled oscillator are optimized emphasically.When the charge pump is designed,the works we did to reduce non-ideal characteristics including increasing the area of the MOS device,using cascode structure and designing an extra circuit for suppressing charge sharing.When designing the voltage controlled oscillator,the output jitter performance of the voltage controlled oscillator is improved by adding a power supply suppression circuit and increasing the junction capacitance.Finally,a fast-locking and low-jitter clock and data recovery circuit is obtained.The maximum lock time of the PLL loop is 15?s,and the maximum time for switching to the CDR loop is 64?s.In the case of power supply plus ripple,of which peak-to-peak amplitude is 150 m V and frequency is 1MHz,when the data transmission rate is 160 Mbps,the maximum output jitter is 54 ps,and when the data transmission rate is 330 Mbps,the maximum output jitter is 57 ps.