Research And Chip Design Of Charge-pump Phase-Locked Loop Based On CMOS Technology

Since the independent establishment of the Bei Dou Satellite Navigation System by China at the beginning of this century,the research and design of navigation system chips have become one of the hottest topics in academia and industry.For the end users of navigation systems,the receiver is an essential carrier,and the local oscillator signal,as a key element for signal demodulation and positioning in the receiver,plays a crucial role in the positioning ability of the navigation receiver due to its stability and frequency precision.The charge pump phase-locked loop,as a type of frequency synthesizer,with advantages such as strong noise resistance and wide frequency locking range,is often used to provide local oscillator signals for RF circuits,including navigation receivers.This thesis first investigates the academic literature in the field of phase-locked loops at home and abroad based on an understanding of the working principles and application scenarios of charge pump PLLs,and summarizes the latest research results.Secondly,on the premise of understanding the basic principles of charge pump PLLs,the linear model and noise model of PLLs are further studied and analyzed.Based on this,a portable loop filter parameter calculation APP is designed on the MATLAB platform,and a Simulink simulation model of the charge pump PLL is built.In addition,based on the influence of each module of the PLL on the overall performance,a high-gain constant trans-conductance rail-to-rail operational amplifier circuit with an operational amplifier gain between 82 and 85 d B and phase margin of around 62 degrees is designed and studied to improve the non-ideal effects of charge pumps.A charge pump circuit is also proposed and implemented,which has good current matching throughout the output range of the working voltage and can be used to reduce the reference spurs of the PLL.Finally,based on the application requirements of quadrature local oscillator signals in RF transceivers and in-depth analysis of the theory of phase noise of voltage-controlled oscillators,a quadrature voltage-controlled oscillator with four orthogonal equidistant outputs is designed and implemented.This thesis presents a design and implementation of a CMOS charge pump phase-locked loop using TSMC 0.18μm process technology,based on the understanding of the basic principles of PLL and the application requirements of charge pump PLL frequency synthesizers.The output frequency range of the PLL covers 1.05～1.95 GHz,and the current mismatch of the charge pump with a working current of 100μA is less than0.15%,and the reference spur is-66.3d Bc.The phase noise of the the quadrature-voltage controlled oscillator is-127.37 d Bc/Hz@1MHz when it operating at the center frequency of1.571 GHz.The maximum division ratio of a programmable multi-mode frequency divider is 120.