Research And Design Of A Continuous-rate Based-PLL Clock And Data Recovery Circuit

Serial communications are the primary means of data communications currently using, and itscrucial part of the data receiver is CDR (Clock and Data Recovery) circuit, whose performancedetermines the overall performance of the receiver. So far, an important development trend of CDRtechnology is to adapt to some occasions in needs of multiple-bit-rate or continuous-rate. Therefore,in this paper, focusing on the continuous-rate CDR based on PLL (Phase-locked Loop), variousrelated modules were discussed, such as the PFD (Phase Frequency Detector), the Multi-band ringVCO (Voltage-Controlled Oscillator), the CP (Charge Pump) and so on.A622~3125Mbps full-rate CDR is designed in0.18μm CMOS process. The CDR circuitmainly include a full-rate bang-bang PFD, a Multi-band ring VCO, two CPs and other modules.Among them, the full-rate PFD not only has a good function, but also makes the simple structure,lower power consumption and area. The multi-band ring VCO not only over a wide tuning range,but also into the tuning loop gain is relatively low, it could deal with the conflict between highoscillating frequency and low tuning gain. The Using bootstrap CP reference and the op ampreduces various non-ideal factors. Simulation results showed that the circuit is working properly, theCDR circuit can recover the PRBS (Pseudo Random Bit Stream) data from622to3125Mbps. Thecore size is700μm×421μm, at1.8V supply voltage, the input PRBS data rate3125Mbps, thepower consumption is100.8mW, the recovered data and clock jitter peak was5.38ps and4.81ps.A622~3125Mbps half-rate CDR is designed in0.18μm CMOS process, which is mainlycomposed of a half-rate bang-bang PFD, a multi-band ring VCO, two CPs, a parallel decisioncircuit and other blocks. Among them, the half-rate PFD consists of four double-edge flip-flops,which has a low complexity, so both the power consumption and die area a re reduced accordingly.Both a wide tuning range and a low tuning gain are satisfied by the Multi-band ring VCO, whichcould deal with the conflict between a high oscillating frequency and a low tuning gain. Variousnon-ideal effects are reduced by the CP with a gain-boosted cascode amplifier and acomplementary-switch structure. Besides, the parallel decision circuit has the function of a1:2demultipexer. Finally, simulation results showed that the CDR can recover the PRBS data from622to3125Mbps. The core size is800μm×687μm. From1.8V supply voltage, when a PRBS data of3125Mbps is applied, the120mW power is consumed, and the peak-to-peak jitter of the recovered data and clock are5.18ps and4.41ps, respectively.