High-performance Phase-locked Loop For High-speed Adc Clock System

Analog-to-Digital converters (ADCs) are developing very rapidly recently as the interface between the nature and the modern digital processed systems, with the flying progress of the telecommunication, the digital signal processing and the semiconductor manufacturing technologies. While the sampling rate and the resolution of ADCs become higher and higher, however, the aperture uncertainty affected by the clock jitter will cause the sampling dots shift more and more seriously, inducing the decrease of the SNR of the Sample and Hold (S/H) circuit, which restrains the ADCs'performance enhancement sharply. Thus a Phase-Locked Loop (PLL) is needed to generate more stable and accurate clock signals on chip.This thesis starts at the study of a Phase-Locked Loop applied to the clock system of a 12Bit 100MSPS pipelined ADC, and the deep analysis of the low jitter single output frequency PLL is unfolded from basic principles, system level design, transistor circuits design and layouts design.Firstly, the PLL's open-loop and closed-loop transfer functions are gained based on the analysis of whose linear s-domain model. Then the phase noise sources in the loop and their transfer characteristics are studied carefully.Secondly, the relationships between PLL's circuit parameters and his closed-loop characteristics are obtained through the approximate second-order analysis, and the loop parameters are chosen optimumly according to the guideline, then all the resistors and capacitances of the loop filter are calculated without any approximation. At last the PLL's system level model and simulation are made using the Simulink tools in the Matlab environment.Thirdly, the depress methods of those unideal effects of PFD and CP are researched, and the key modules, including PFD, CP, VCO and divider are designed based on SMIC 0.18μm CMOS mixed-signal process. After that, the simulation results of the whole PLL circuit show that the locking time is about 17μs at the 1.8V power supply, the 25℃and the TT process corner. There is little ripple on the VCO's controlling voltage when the PLL is locked in, which indicates that the PFD's"dead zone"has been eliminated, the unideal effects of CP have also been depressed efficiently, and the linearity of the VCO is good with the centre output frequency of 200MHz. The power dissipation of the whole circuits is 14.6mW when the power supply is 1.8V. In addition, the PLL is simulated under different process corners, temperatures and supply voltages. The simulation results show that it can operate well under all these PVT conditions.In the end, condisering the devices matching, the circuit symmetry and the protecting of sensitive blocks adequately, the PLL's layout is drew using the Virtuoso tools in the Cadence environment. It has a total area of 520μm×380μm.