Research On Column-parallel Fully Differential SAR/SS ADC In CMOS Image Sensor

CMOS image sensor(CIS)technology has been rapidly developed,but the research of high frame rate,high resolution,large dynamic range and small area CMOS image sensor still faces enormous challenges.Column-parallel Analog to Digital Converter(ADC)as a key module always determines the performance of CMOS image sensors.it puts forward higher requirements for column parallel ADC in aspects of high speed,high precision,small area and low power consumption.Through analyzing and comparing the several columns parallel ADC structure,this paper presents a 12-bit fully-differential two-step SAR/SS ADC which combins the advantages of the successive approximation register(SAR)ADC and single slope(SS)ADC.The high 6-bit ADC and low 6-bit ADC adopt SAR ADC and SS ADC structures respectively,which avoids the problem of excessive area caused by the SAR ADC and increases the conversion speed of the SS ADC,making a good compromise between speed and area.The input of the ADC uses a differential sampling circuit that eliminates the fixed offset of the sampling switch,reduces nonlinear errors and improves the signal to noise ratio.The SAR ADC is quantized with a high 6-bit,and 2+4 split capacitor arrays reduce the area of capacitor arrays.The new switch control timing sequence reduces the variation range of common mode level and the influence of common mode level on comparator.The SS ADC is quantized with a low 6-bits,the current steering DAC simultaneously outputs a rising ramp and a falling ramp with differential characteristics.The SAR ADC and SS ADC share a comparator to save power and area.The fully differential two-step SAR/SS ADC is designed and implemented by UMC 0.11μm CMOS process.The circuit schematic design,layout design and post-simulation verification are completed by tools such as Cadence and Matlab.The digital and analog supply voltages of the ADC are 1.2V and 3.3V respectively,and the quantization voltage range is 0-2 V.The ADC has the differential nonlinearity of-0.25/+0.25 LSB and the integral nonlinearity of-0.38/+0.56 LSB.The signal-to-noise distortion ratio is 67.9 dB,and the effective number of bits is 10.9 bits at the sampling rate of 227 kS/s when the input frequency is 11.0 kHz.It satisfies the performance requirements of CMOS image sensors.