Study And Design Of The Analog-to-digital Converter For CMOS Image Sensor Chip

In recent years,CMOS image sensor(CIS)has replaced Charge-Coupled Device(CCD)detector due to its fast development in process and image quality.A typical CIS system is mainly composed of a pixel array,a row scanner controller,column-parallel analog-to-digital converters(ADCs)and digital interfaces,where the column ADCs are the key module to determine the frame rate and resolution of a CIS.Therefore,this paper proposes a CMOS image sensor used for imaging spectrometer for space exploration filed based on the research of the ADC technology.The chip adopts a 14-bit column-paralled successive approximation analog-to-digital converter(SAR ADC)at the sampling rate of 600 KSps with a input voltage range between 0.8 V and 2 V.This paper starts with a brief introduction to the development history and background konwledge of CIS.By comparing the advantages and disadvantages of different column ADC architecture,this paper theoretically proves the feasibility of SAR ADC with multi-voltage references.The designed column-parallel ADC employs a single-ended input capacitor digitial-to-analog converter(CDAC)with four voltage references.Each ADC includes a input buffer,a 7-bit CDAC,a comparator and successive approximation logic,which is designed by using SMIC's 0.18 ?m 3.3 V mixed process.To assure the precision of the ADC,this paper proposes a novel foreground digital calibration scheme to self-trim the on-chip voltage references after system power up,which simplifies the system application and cut down the area and cost.Simulation results show that both the INL and DNL of the proposed SAR ADC after optimization design are within 0.5 LSB.The function of voltage references self-calibration has been verified and the error of the voltage reference is less than 0.22 LSB.The simulation results prove the feasibility of SAR ADC with four voltage references used for CIS.The layout design has also been finished and the area of the ADC is 50 ?m × 2271 ?m.Moreover,the chip package and test results shows the function is good and the basic parameter meet the design target.The column-parallel ADC has an ENOB of 10?11 at the sampling rate of 500 KSps according to the static performace test results.Besides,the CMOS image sensor functions well at the frame rate of 271 fps.