| The advent of the era of artificial intelligence has led to the rapid development of image-centric technologies such as intelligent assisted driving and intelligent manufacturing,placing higher requirements on the performance of image acquisition devices.CMOS image sensors are widely used in the field of image acquisition due to their high integration,low power consumption,and compatibility with standard CMOS manufacturing processes.This thesis theoretically analyzes the pixels and readout circuits of image sensors,and designs a readout circuit for CMOS image sensors from the perspectives of power consumption,speed,and area.The main work of this thesis is as follows:Firstly,the ADC circuits commonly used in CMOS image sensors are investigated and analyzed.Currently,ADCs that are widely used are mainly divided into column level,pixel level,and chip level according to their working methods;According to the type of ADC,it is mainly divided into Single-Slope ADC(SS ADC),Successive Approximation Register ADC(SAR ADC),and Cyclic ADC.Combining the characteristics of the ADC described above,the column level Successive Approximation Register ADC is finally selected as the ADC of the readout circuit in this thesis.Secondly,the commonly used pixel units in CMOS image sensors have been investigated and analyzed.Currently,the main commonly used pixels include 3T-APS,4T-APS,and 5T-APS.Combining the characteristics of the image sensor designed in this thesis,a 5T pixel unit has been designed.By changing the capacitance of the FD point,the sensor can obtain different conversion gains under dark and bright light conditions..The final designed pixel output noise is 82 μV and power consumption is 47 n W.Finally,a single-ended input column level SAR ADC operating at a 1.2V power supply voltage with an accuracy of 12 bits and a sampling rate of 800 KS/s was designed under a 55 nm CMOS process,meeting the requirements of a resolution of 1.3 million,a frame rate of 60 fps,and supporting DCG mode output.SAR ADC consists of a comparator,SAR Logic,registers,DAC,and other modules.The DAC adopts a segmented capacitive DAC structure to reduce the area and power consumption of the DAC array.The designed comparator uses a preamplifier and latch structure to reduce noise.The layout and post simulation of the designed Column-Level SAR ADC are performed.The simulation results show that the effective bit of the designed SAR ADC is 9.7 bits,the SFDR is 68.5d B,the DNL and INL are-1.5/+0.99 LSB,-1.2/+1.4 LSB,and the power consumption is 17 μW. |
